mirror of https://github.com/proxmox/mirror_qemu
target-arm: Implement AArch64 CurrentEL sysreg
Implement the CurrentEL sysreg. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>master
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7da845b0f4
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0eef9d9833
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@ -731,7 +731,8 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
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#define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
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#define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
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#define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
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#define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
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#define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8))
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#define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8))
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#define ARM_LAST_SPECIAL ARM_CP_NZCV
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#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8))
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#define ARM_LAST_SPECIAL ARM_CP_CURRENTEL
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/* Used only as a terminator for ARMCPRegInfo lists */
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/* Used only as a terminator for ARMCPRegInfo lists */
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#define ARM_CP_SENTINEL 0xffff
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#define ARM_CP_SENTINEL 0xffff
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/* Mask of only the flag bits in a type field */
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/* Mask of only the flag bits in a type field */
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@ -1533,6 +1533,9 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
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.opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
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.opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
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.access = PL0_R, .type = ARM_CP_CONST,
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.access = PL0_R, .type = ARM_CP_CONST,
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.resetvalue = 0x10 },
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.resetvalue = 0x10 },
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{ .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
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.access = PL1_R, .type = ARM_CP_CURRENTEL },
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REGINFO_SENTINEL
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REGINFO_SENTINEL
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};
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};
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@ -1231,6 +1231,13 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
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gen_set_nzcv(tcg_rt);
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gen_set_nzcv(tcg_rt);
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}
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}
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return;
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return;
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case ARM_CP_CURRENTEL:
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/* Reads as current EL value from pstate, which is
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* guaranteed to be constant by the tb flags.
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*/
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tcg_rt = cpu_reg(s, rt);
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tcg_gen_movi_i64(tcg_rt, s->current_pl << 2);
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return;
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default:
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default:
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break;
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break;
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}
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}
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