mirror of https://github.com/proxmox/mirror_qemu
libqos: Use explicit QTestState for ahci operations
Drop one more client of global_qtest by teaching all ahci test functionality to pass in an explicit QTestState. The state was already available, so no callers had to be adjusted. Signed-off-by: Eric Blake <eblake@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>master
Eric Blake
Thomas Huth
parent
f1dfd50732
commit
10747e55d5
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@ -283,7 +283,8 @@ void ahci_hba_enable(AHCIQState *ahci)
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/* Allocate Memory for the Command List Buffer & FIS Buffer */
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/* PxCLB space ... 0x20 per command, as in 4.2.2 p 36 */
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ahci->port[i].clb = ahci_alloc(ahci, num_cmd_slots * 0x20);
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qmemset(ahci->port[i].clb, 0x00, num_cmd_slots * 0x20);
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qtest_memset(ahci->parent->qts, ahci->port[i].clb, 0x00,
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num_cmd_slots * 0x20);
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g_test_message("CLB: 0x%08" PRIx64, ahci->port[i].clb);
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ahci_px_wreg(ahci, i, AHCI_PX_CLB, ahci->port[i].clb);
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g_assert_cmphex(ahci->port[i].clb, ==,
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@ -291,7 +292,7 @@ void ahci_hba_enable(AHCIQState *ahci)
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/* PxFB space ... 0x100, as in 4.2.1 p 35 */
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ahci->port[i].fb = ahci_alloc(ahci, 0x100);
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qmemset(ahci->port[i].fb, 0x00, 0x100);
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qtest_memset(ahci->parent->qts, ahci->port[i].fb, 0x00, 0x100);
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g_test_message("FB: 0x%08" PRIx64, ahci->port[i].fb);
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ahci_px_wreg(ahci, i, AHCI_PX_FB, ahci->port[i].fb);
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g_assert_cmphex(ahci->port[i].fb, ==,
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@ -397,7 +398,7 @@ void ahci_port_clear(AHCIQState *ahci, uint8_t port)
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g_assert_cmphex(ahci_px_rreg(ahci, port, AHCI_PX_IS), ==, 0);
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/* Wipe the FIS-Receive Buffer */
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qmemset(ahci->port[port].fb, 0x00, 0x100);
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qtest_memset(ahci->parent->qts, ahci->port[port].fb, 0x00, 0x100);
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}
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/**
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@ -466,7 +467,7 @@ void ahci_port_check_d2h_sanity(AHCIQState *ahci, uint8_t port, uint8_t slot)
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RegD2HFIS *d2h = g_malloc0(0x20);
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uint32_t reg;
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memread(ahci->port[port].fb + 0x40, d2h, 0x20);
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qtest_memread(ahci->parent->qts, ahci->port[port].fb + 0x40, d2h, 0x20);
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g_assert_cmphex(d2h->fis_type, ==, 0x34);
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reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
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@ -484,7 +485,7 @@ void ahci_port_check_pio_sanity(AHCIQState *ahci, uint8_t port,
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/* We cannot check the Status or E_Status registers, because
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* the status may have again changed between the PIO Setup FIS
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* and the conclusion of the command with the D2H Register FIS. */
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memread(ahci->port[port].fb + 0x20, pio, 0x20);
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qtest_memread(ahci->parent->qts, ahci->port[port].fb + 0x20, pio, 0x20);
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g_assert_cmphex(pio->fis_type, ==, 0x5f);
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/* BUG: PIO Setup FIS as utilized by QEMU tries to fit the entire
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@ -516,7 +517,7 @@ void ahci_get_command_header(AHCIQState *ahci, uint8_t port,
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{
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uint64_t ba = ahci->port[port].clb;
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ba += slot * sizeof(AHCICommandHeader);
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memread(ba, cmd, sizeof(AHCICommandHeader));
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qtest_memread(ahci->parent->qts, ba, cmd, sizeof(AHCICommandHeader));
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cmd->flags = le16_to_cpu(cmd->flags);
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cmd->prdtl = le16_to_cpu(cmd->prdtl);
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@ -537,7 +538,7 @@ void ahci_set_command_header(AHCIQState *ahci, uint8_t port,
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tmp.prdbc = cpu_to_le32(cmd->prdbc);
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tmp.ctba = cpu_to_le64(cmd->ctba);
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memwrite(ba, &tmp, sizeof(AHCICommandHeader));
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qtest_memwrite(ahci->parent->qts, ba, &tmp, sizeof(AHCICommandHeader));
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}
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void ahci_destroy_command(AHCIQState *ahci, uint8_t port, uint8_t slot)
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@ -575,7 +576,7 @@ void ahci_write_fis(AHCIQState *ahci, AHCICommand *cmd)
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tmp.count = cpu_to_le16(tmp.count);
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}
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memwrite(addr, &tmp, sizeof(tmp));
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qtest_memwrite(ahci->parent->qts, addr, &tmp, sizeof(tmp));
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}
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unsigned ahci_pick_cmd(AHCIQState *ahci, uint8_t port)
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@ -636,7 +637,7 @@ void ahci_exec(AHCIQState *ahci, uint8_t port,
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if (opts->size && !opts->buffer) {
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opts->buffer = ahci_alloc(ahci, opts->size);
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g_assert(opts->buffer);
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qmemset(opts->buffer, 0x00, opts->size);
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qtest_memset(ahci->parent->qts, opts->buffer, 0x00, opts->size);
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}
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/* Command creation */
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@ -661,15 +662,15 @@ void ahci_exec(AHCIQState *ahci, uint8_t port,
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ahci_command_commit(ahci, cmd, port);
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ahci_command_issue_async(ahci, cmd);
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if (opts->error) {
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qmp_eventwait("STOP");
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qtest_qmp_eventwait(ahci->parent->qts, "STOP");
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}
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if (opts->mid_cb) {
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rc = opts->mid_cb(ahci, cmd, opts);
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g_assert_cmpint(rc, ==, 0);
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}
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if (opts->error) {
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qmp_async("{'execute':'cont' }");
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qmp_eventwait("RESUME");
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qtest_async_qmp(ahci->parent->qts, "{'execute':'cont' }");
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qtest_qmp_eventwait(ahci->parent->qts, "RESUME");
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}
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/* Wait for command to complete and verify sanity */
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@ -697,7 +698,7 @@ AHCICommand *ahci_guest_io_halt(AHCIQState *ahci, uint8_t port,
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ahci_command_adjust(cmd, sector, buffer, bufsize, 0);
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ahci_command_commit(ahci, cmd, port);
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ahci_command_issue_async(ahci, cmd);
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qmp_eventwait("STOP");
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qtest_qmp_eventwait(ahci->parent->qts, "STOP");
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return cmd;
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}
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@ -706,8 +707,8 @@ AHCICommand *ahci_guest_io_halt(AHCIQState *ahci, uint8_t port,
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void ahci_guest_io_resume(AHCIQState *ahci, AHCICommand *cmd)
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{
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/* Complete the command */
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qmp_async("{'execute':'cont' }");
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qmp_eventwait("RESUME");
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qtest_async_qmp(ahci->parent->qts, "{'execute':'cont' }");
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qtest_qmp_eventwait(ahci->parent->qts, "RESUME");
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ahci_command_wait(ahci, cmd);
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ahci_command_verify(ahci, cmd);
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ahci_command_free(cmd);
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@ -754,16 +755,16 @@ void ahci_io(AHCIQState *ahci, uint8_t port, uint8_t ide_cmd,
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g_assert(props);
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ptr = ahci_alloc(ahci, bufsize);
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g_assert(!bufsize || ptr);
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qmemset(ptr, 0x00, bufsize);
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qtest_memset(ahci->parent->qts, ptr, 0x00, bufsize);
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if (bufsize && props->write) {
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bufwrite(ptr, buffer, bufsize);
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qtest_bufwrite(ahci->parent->qts, ptr, buffer, bufsize);
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}
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ahci_guest_io(ahci, port, ide_cmd, ptr, bufsize, sector);
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if (bufsize && props->read) {
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bufread(ptr, buffer, bufsize);
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qtest_bufread(ahci->parent->qts, ptr, buffer, bufsize);
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}
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ahci_free(ahci, ptr);
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@ -901,7 +902,7 @@ static int copy_buffer(AHCIQState *ahci, AHCICommand *cmd,
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const AHCIOpts *opts)
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{
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unsigned char *rx = opts->opaque;
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bufread(opts->buffer, rx, opts->size);
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qtest_bufread(ahci->parent->qts, opts->buffer, rx, opts->size);
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return 0;
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}
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@ -1141,7 +1142,7 @@ void ahci_command_commit(AHCIQState *ahci, AHCICommand *cmd, uint8_t port)
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ahci_write_fis(ahci, cmd);
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/* Then ATAPI CMD, if needed */
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if (cmd->props->atapi) {
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memwrite(table_ptr + 0x40, cmd->atapi_cmd, 16);
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qtest_memwrite(ahci->parent->qts, table_ptr + 0x40, cmd->atapi_cmd, 16);
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}
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/* Construct and write the PRDs to the command table */
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@ -1162,8 +1163,8 @@ void ahci_command_commit(AHCIQState *ahci, AHCICommand *cmd, uint8_t port)
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prd.dbc |= cpu_to_le32(0x80000000); /* Request DPS Interrupt */
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/* Commit the PRD entry to the Command Table */
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memwrite(table_ptr + 0x80 + (i * sizeof(PRD)),
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&prd, sizeof(PRD));
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qtest_memwrite(ahci->parent->qts, table_ptr + 0x80 + (i * sizeof(PRD)),
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&prd, sizeof(PRD));
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}
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/* Bookmark the PRDTL and CTBA values */
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