diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 7cacb56bc5..aa1d013c31 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -119,6 +119,9 @@ enum powerpc_mmu_t { /* Architecture 2.06 variant */ POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | POWERPC_MMU_AMR | 0x00000003, + /* Architecture 2.06 "degraded" (no 1T segments) */ + POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR + | 0x00000003, /* Architecture 2.06 "degraded" (no 1T segments or AMR) */ POWERPC_MMU_2_06d = POWERPC_MMU_64 | 0x00000003, #endif /* defined(TARGET_PPC64) */ diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index acf01331f1..68d5415e54 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -1188,6 +1188,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env) #if defined(TARGET_PPC64) case POWERPC_MMU_64B: case POWERPC_MMU_2_06: + case POWERPC_MMU_2_06a: case POWERPC_MMU_2_06d: dump_slb(f, cpu_fprintf, env); break; @@ -1324,6 +1325,7 @@ hwaddr cpu_get_phys_page_debug(CPUPPCState *env, target_ulong addr) #if defined(TARGET_PPC64) case POWERPC_MMU_64B: case POWERPC_MMU_2_06: + case POWERPC_MMU_2_06a: case POWERPC_MMU_2_06d: return ppc_hash64_get_phys_page_debug(env, addr); #endif @@ -1815,6 +1817,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) #if defined(TARGET_PPC64) case POWERPC_MMU_64B: case POWERPC_MMU_2_06: + case POWERPC_MMU_2_06a: case POWERPC_MMU_2_06d: #endif /* defined(TARGET_PPC64) */ tlb_flush(env, 1); @@ -1884,6 +1887,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) #if defined(TARGET_PPC64) case POWERPC_MMU_64B: case POWERPC_MMU_2_06: + case POWERPC_MMU_2_06a: case POWERPC_MMU_2_06d: /* tlbie invalidate TLBs for all segments */ /* XXX: given the fact that there are too many segments to invalidate,