mirror of https://github.com/proxmox/mirror_qemu
target/openrisc: Make openrisc_cpu_tlb_fill sysemu only
The fallback code in cpu_loop_exit_sigsegv is sufficient for openrisc linux-user. This makes all of the code in mmu.c sysemu only, so remove the ifdefs and move the file to openrisc_softmmu_ss. Remove the code from cpu_loop that handled EXCP_DPF. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>master
parent
d315712b69
commit
12f0bc5579
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@ -54,14 +54,6 @@ void cpu_loop(CPUOpenRISCState *env)
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cpu_set_gpr(env, 11, ret);
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cpu_set_gpr(env, 11, ret);
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}
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}
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break;
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break;
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case EXCP_DPF:
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case EXCP_IPF:
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info.si_signo = TARGET_SIGSEGV;
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info.si_errno = 0;
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info.si_code = TARGET_SEGV_MAPERR;
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info._sifields._sigfault._addr = env->pc;
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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break;
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case EXCP_ALIGN:
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case EXCP_ALIGN:
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info.si_signo = TARGET_SIGBUS;
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info.si_signo = TARGET_SIGBUS;
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info.si_errno = 0;
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info.si_errno = 0;
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@ -186,9 +186,9 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = {
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static const struct TCGCPUOps openrisc_tcg_ops = {
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static const struct TCGCPUOps openrisc_tcg_ops = {
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.initialize = openrisc_translate_init,
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.initialize = openrisc_translate_init,
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.tlb_fill = openrisc_cpu_tlb_fill,
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#ifndef CONFIG_USER_ONLY
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#ifndef CONFIG_USER_ONLY
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.tlb_fill = openrisc_cpu_tlb_fill,
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.cpu_exec_interrupt = openrisc_cpu_exec_interrupt,
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.cpu_exec_interrupt = openrisc_cpu_exec_interrupt,
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.do_interrupt = openrisc_cpu_do_interrupt,
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.do_interrupt = openrisc_cpu_do_interrupt,
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#endif /* !CONFIG_USER_ONLY */
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#endif /* !CONFIG_USER_ONLY */
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@ -317,14 +317,15 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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void openrisc_translate_init(void);
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void openrisc_translate_init(void);
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bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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int print_insn_or1k(bfd_vma addr, disassemble_info *info);
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int print_insn_or1k(bfd_vma addr, disassemble_info *info);
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#define cpu_list cpu_openrisc_list
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#define cpu_list cpu_openrisc_list
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#ifndef CONFIG_USER_ONLY
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#ifndef CONFIG_USER_ONLY
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bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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extern const VMStateDescription vmstate_openrisc_cpu;
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extern const VMStateDescription vmstate_openrisc_cpu;
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void openrisc_cpu_do_interrupt(CPUState *cpu);
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void openrisc_cpu_do_interrupt(CPUState *cpu);
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@ -10,7 +10,6 @@ openrisc_ss.add(files(
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'fpu_helper.c',
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'fpu_helper.c',
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'gdbstub.c',
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'gdbstub.c',
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'interrupt_helper.c',
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'interrupt_helper.c',
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'mmu.c',
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'sys_helper.c',
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'sys_helper.c',
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'translate.c',
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'translate.c',
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))
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))
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@ -19,6 +18,7 @@ openrisc_softmmu_ss = ss.source_set()
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openrisc_softmmu_ss.add(files(
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openrisc_softmmu_ss.add(files(
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'interrupt.c',
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'interrupt.c',
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'machine.c',
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'machine.c',
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'mmu.c',
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))
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))
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target_arch += {'openrisc': openrisc_ss}
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target_arch += {'openrisc': openrisc_ss}
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@ -23,11 +23,8 @@
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#include "exec/exec-all.h"
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#include "exec/exec-all.h"
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#include "exec/gdbstub.h"
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#include "exec/gdbstub.h"
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#include "qemu/host-utils.h"
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#include "qemu/host-utils.h"
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#ifndef CONFIG_USER_ONLY
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#include "hw/loader.h"
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#include "hw/loader.h"
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#endif
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#ifndef CONFIG_USER_ONLY
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static inline void get_phys_nommu(hwaddr *phys_addr, int *prot,
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static inline void get_phys_nommu(hwaddr *phys_addr, int *prot,
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target_ulong address)
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target_ulong address)
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{
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{
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@ -94,7 +91,6 @@ static int get_phys_mmu(OpenRISCCPU *cpu, hwaddr *phys_addr, int *prot,
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return need & PAGE_EXEC ? EXCP_ITLBMISS : EXCP_DTLBMISS;
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return need & PAGE_EXEC ? EXCP_ITLBMISS : EXCP_DTLBMISS;
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}
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}
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}
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}
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#endif
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static void raise_mmu_exception(OpenRISCCPU *cpu, target_ulong address,
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static void raise_mmu_exception(OpenRISCCPU *cpu, target_ulong address,
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int exception)
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int exception)
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@ -112,8 +108,6 @@ bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
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{
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{
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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int excp = EXCP_DPF;
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int excp = EXCP_DPF;
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#ifndef CONFIG_USER_ONLY
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int prot;
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int prot;
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hwaddr phys_addr;
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hwaddr phys_addr;
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@ -138,13 +132,11 @@ bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
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if (probe) {
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if (probe) {
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return false;
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return false;
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}
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}
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#endif
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raise_mmu_exception(cpu, addr, excp);
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raise_mmu_exception(cpu, addr, excp);
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cpu_loop_exit_restore(cs, retaddr);
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cpu_loop_exit_restore(cs, retaddr);
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}
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}
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#ifndef CONFIG_USER_ONLY
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hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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{
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{
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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@ -177,4 +169,3 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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return phys_addr;
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return phys_addr;
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}
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}
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}
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}
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#endif
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