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target-arm: A64: add support for ADR and ADRP 

Add support for the instructions described in
"C3.4.6 PC-rel. addressing" (ADR and ADRP).

Signed-off-by: Alexander Graf <agraf@suse.de>
[claudio: adapted to new decoder structure]
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
master
Alexander Graf 2013-12-17 19:42:34 +00:00 committed by Peter Maydell
parent 832ffa1ce0
commit 15bfe8b650
1 changed files with 23 additions and 2 deletions
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25
target-arm/translate-a64.c
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@ -653,10 +653,31 @@ static void disas_ldst(DisasContext *s, uint32_t insn)
}
}
/* PC-rel. addressing */
/* C3.4.6 PC-rel. addressing
* 31 30 29 28 24 23 5 4 0
* +----+-------+-----------+-------------------+------+
* | op | immlo | 1 0 0 0 0 | immhi | Rd |
* +----+-------+-----------+-------------------+------+
*/
static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
{
unsupported_encoding(s, insn);
unsigned int page, rd;
uint64_t base;
int64_t offset;
page = extract32(insn, 31, 1);
/* SignExtend(immhi:immlo) -> offset */
offset = ((int64_t)sextract32(insn, 5, 19) << 2) | extract32(insn, 29, 2);
rd = extract32(insn, 0, 5);
base = s->pc - 4;
if (page) {
/* ADRP (page based) */
base &= ~0xfff;
offset <<= 12;
}
tcg_gen_movi_i64(cpu_reg(s, rd), base + offset);
}
/* Add/subtract (immediate) */