mirror of https://github.com/proxmox/mirror_qemu
leon3: introduce the plug and play mechanism
This adds the AHB and APB plug and play devices. They are scanned during the linux boot to discover the various peripheral. Reviewed-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>master
KONRAD Frederic
Mark Cave-Ayland
parent
dbed0d2d2a
commit
162abf1a83
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@ -1161,7 +1161,7 @@ M: Fabien Chouteau <chouteau@adacore.com>
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S: Maintained
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F: hw/sparc/leon3.c
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F: hw/*/grlib*
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F: include/hw/sparc/grlib.h
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F: include/hw/*/grlib*
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S390 Machines
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-------------
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@ -77,3 +77,5 @@ obj-$(CONFIG_AUX) += auxbus.o
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obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o
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obj-$(CONFIG_MSF2) += msf2-sysreg.o
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obj-$(CONFIG_NRF51_SOC) += nrf51_rng.o
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obj-$(CONFIG_GRLIB) += grlib_ahb_apb_pnp.o
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@ -0,0 +1,269 @@
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/*
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* GRLIB AHB APB PNP
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*
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* Copyright (C) 2019 AdaCore
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*
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* Developed by :
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* Frederic Konrad <frederic.konrad@adacore.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "hw/misc/grlib_ahb_apb_pnp.h"
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#define GRLIB_PNP_VENDOR_SHIFT (24)
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#define GRLIB_PNP_VENDOR_SIZE (8)
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#define GRLIB_PNP_DEV_SHIFT (12)
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#define GRLIB_PNP_DEV_SIZE (12)
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#define GRLIB_PNP_VER_SHIFT (5)
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#define GRLIB_PNP_VER_SIZE (5)
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#define GRLIB_PNP_IRQ_SHIFT (0)
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#define GRLIB_PNP_IRQ_SIZE (5)
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#define GRLIB_PNP_ADDR_SHIFT (20)
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#define GRLIB_PNP_ADDR_SIZE (12)
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#define GRLIB_PNP_MASK_SHIFT (4)
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#define GRLIB_PNP_MASK_SIZE (12)
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#define GRLIB_AHB_DEV_ADDR_SHIFT (20)
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#define GRLIB_AHB_DEV_ADDR_SIZE (12)
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#define GRLIB_AHB_ENTRY_SIZE (0x20)
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#define GRLIB_AHB_MAX_DEV (64)
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#define GRLIB_AHB_SLAVE_OFFSET (0x800)
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#define GRLIB_APB_DEV_ADDR_SHIFT (8)
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#define GRLIB_APB_DEV_ADDR_SIZE (12)
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#define GRLIB_APB_ENTRY_SIZE (0x08)
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#define GRLIB_APB_MAX_DEV (512)
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#define GRLIB_PNP_MAX_REGS (0x1000)
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typedef struct AHBPnp {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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uint32_t regs[GRLIB_PNP_MAX_REGS >> 2];
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uint8_t master_count;
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uint8_t slave_count;
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} AHBPnp;
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void grlib_ahb_pnp_add_entry(AHBPnp *dev, uint32_t address, uint32_t mask,
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uint8_t vendor, uint16_t device, int slave,
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int type)
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{
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unsigned int reg_start;
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/*
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* AHB entries look like this:
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*
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* 31 -------- 23 -------- 11 ----- 9 -------- 4 --- 0
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* | VENDOR ID | DEVICE ID | IRQ ? | VERSION | IRQ |
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* --------------------------------------------------
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* | USER |
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* --------------------------------------------------
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* | USER |
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* --------------------------------------------------
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* | USER |
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* --------------------------------------------------
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* | USER |
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* --------------------------------------------------
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* 31 ----------- 20 --- 15 ----------------- 3 ---- 0
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* | ADDR[31..12] | 00PC | MASK | TYPE |
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* --------------------------------------------------
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* 31 ----------- 20 --- 15 ----------------- 3 ---- 0
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* | ADDR[31..12] | 00PC | MASK | TYPE |
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* --------------------------------------------------
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* 31 ----------- 20 --- 15 ----------------- 3 ---- 0
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* | ADDR[31..12] | 00PC | MASK | TYPE |
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* --------------------------------------------------
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* 31 ----------- 20 --- 15 ----------------- 3 ---- 0
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* | ADDR[31..12] | 00PC | MASK | TYPE |
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* --------------------------------------------------
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*/
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if (slave) {
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assert(dev->slave_count < GRLIB_AHB_MAX_DEV);
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reg_start = (GRLIB_AHB_SLAVE_OFFSET
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+ (dev->slave_count * GRLIB_AHB_ENTRY_SIZE)) >> 2;
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dev->slave_count++;
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} else {
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assert(dev->master_count < GRLIB_AHB_MAX_DEV);
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reg_start = (dev->master_count * GRLIB_AHB_ENTRY_SIZE) >> 2;
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dev->master_count++;
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}
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dev->regs[reg_start] = deposit32(dev->regs[reg_start],
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GRLIB_PNP_VENDOR_SHIFT,
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GRLIB_PNP_VENDOR_SIZE,
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vendor);
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dev->regs[reg_start] = deposit32(dev->regs[reg_start],
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GRLIB_PNP_DEV_SHIFT,
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GRLIB_PNP_DEV_SIZE,
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device);
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reg_start += 4;
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/* AHB Memory Space */
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dev->regs[reg_start] = type;
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dev->regs[reg_start] = deposit32(dev->regs[reg_start],
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GRLIB_PNP_ADDR_SHIFT,
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GRLIB_PNP_ADDR_SIZE,
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extract32(address,
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GRLIB_AHB_DEV_ADDR_SHIFT,
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GRLIB_AHB_DEV_ADDR_SIZE));
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dev->regs[reg_start] = deposit32(dev->regs[reg_start],
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GRLIB_PNP_MASK_SHIFT,
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GRLIB_PNP_MASK_SIZE,
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mask);
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}
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static uint64_t grlib_ahb_pnp_read(void *opaque, hwaddr offset, unsigned size)
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{
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AHBPnp *ahb_pnp = GRLIB_AHB_PNP(opaque);
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return ahb_pnp->regs[offset >> 2];
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}
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static const MemoryRegionOps grlib_ahb_pnp_ops = {
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.read = grlib_ahb_pnp_read,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static void grlib_ahb_pnp_realize(DeviceState *dev, Error **errp)
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{
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AHBPnp *ahb_pnp = GRLIB_AHB_PNP(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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memory_region_init_io(&ahb_pnp->iomem, OBJECT(dev), &grlib_ahb_pnp_ops,
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ahb_pnp, TYPE_GRLIB_AHB_PNP, GRLIB_PNP_MAX_REGS);
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sysbus_init_mmio(sbd, &ahb_pnp->iomem);
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}
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static void grlib_ahb_pnp_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = grlib_ahb_pnp_realize;
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}
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static const TypeInfo grlib_ahb_pnp_info = {
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.name = TYPE_GRLIB_AHB_PNP,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(AHBPnp),
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.class_init = grlib_ahb_pnp_class_init,
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};
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/* APBPnp */
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typedef struct APBPnp {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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uint32_t regs[GRLIB_PNP_MAX_REGS >> 2];
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uint32_t entry_count;
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} APBPnp;
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void grlib_apb_pnp_add_entry(APBPnp *dev, uint32_t address, uint32_t mask,
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uint8_t vendor, uint16_t device, uint8_t version,
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uint8_t irq, int type)
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{
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unsigned int reg_start;
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/*
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* APB entries look like this:
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*
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* 31 -------- 23 -------- 11 ----- 9 ------- 4 --- 0
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* | VENDOR ID | DEVICE ID | IRQ ? | VERSION | IRQ |
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*
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* 31 ---------- 20 --- 15 ----------------- 3 ---- 0
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* | ADDR[20..8] | 0000 | MASK | TYPE |
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*/
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assert(dev->entry_count < GRLIB_APB_MAX_DEV);
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reg_start = (dev->entry_count * GRLIB_APB_ENTRY_SIZE) >> 2;
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dev->entry_count++;
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dev->regs[reg_start] = deposit32(dev->regs[reg_start],
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GRLIB_PNP_VENDOR_SHIFT,
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GRLIB_PNP_VENDOR_SIZE,
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vendor);
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dev->regs[reg_start] = deposit32(dev->regs[reg_start],
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GRLIB_PNP_DEV_SHIFT,
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GRLIB_PNP_DEV_SIZE,
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device);
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dev->regs[reg_start] = deposit32(dev->regs[reg_start],
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GRLIB_PNP_VER_SHIFT,
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GRLIB_PNP_VER_SIZE,
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version);
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dev->regs[reg_start] = deposit32(dev->regs[reg_start],
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GRLIB_PNP_IRQ_SHIFT,
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GRLIB_PNP_IRQ_SIZE,
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irq);
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reg_start += 1;
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dev->regs[reg_start] = type;
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dev->regs[reg_start] = deposit32(dev->regs[reg_start],
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GRLIB_PNP_ADDR_SHIFT,
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GRLIB_PNP_ADDR_SIZE,
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extract32(address,
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GRLIB_APB_DEV_ADDR_SHIFT,
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GRLIB_APB_DEV_ADDR_SIZE));
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dev->regs[reg_start] = deposit32(dev->regs[reg_start],
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GRLIB_PNP_MASK_SHIFT,
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GRLIB_PNP_MASK_SIZE,
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mask);
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}
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static uint64_t grlib_apb_pnp_read(void *opaque, hwaddr offset, unsigned size)
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{
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APBPnp *apb_pnp = GRLIB_APB_PNP(opaque);
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return apb_pnp->regs[offset >> 2];
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}
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static const MemoryRegionOps grlib_apb_pnp_ops = {
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.read = grlib_apb_pnp_read,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static void grlib_apb_pnp_realize(DeviceState *dev, Error **errp)
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{
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APBPnp *apb_pnp = GRLIB_APB_PNP(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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memory_region_init_io(&apb_pnp->iomem, OBJECT(dev), &grlib_apb_pnp_ops,
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apb_pnp, TYPE_GRLIB_APB_PNP, GRLIB_PNP_MAX_REGS);
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sysbus_init_mmio(sbd, &apb_pnp->iomem);
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}
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static void grlib_apb_pnp_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = grlib_apb_pnp_realize;
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}
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static const TypeInfo grlib_apb_pnp_info = {
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.name = TYPE_GRLIB_APB_PNP,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(APBPnp),
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.class_init = grlib_apb_pnp_class_init,
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};
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static void grlib_ahb_apb_pnp_register_types(void)
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{
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type_register_static(&grlib_ahb_pnp_info);
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type_register_static(&grlib_apb_pnp_info);
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}
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type_init(grlib_ahb_apb_pnp_register_types)
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@ -39,6 +39,7 @@
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#include "exec/address-spaces.h"
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#include "hw/sparc/grlib.h"
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#include "hw/misc/grlib_ahb_apb_pnp.h"
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/* Default system clock. */
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#define CPU_CLK (40 * 1000 * 1000)
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@ -58,6 +59,9 @@
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#define LEON3_TIMER_IRQ (6)
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#define LEON3_TIMER_COUNT (2)
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#define LEON3_APB_PNP_OFFSET (0x800FF000)
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#define LEON3_AHB_PNP_OFFSET (0xFFFFF000)
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typedef struct ResetData {
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SPARCCPU *cpu;
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uint32_t entry; /* save kernel entry in case of reset */
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@ -187,6 +191,8 @@ static void leon3_generic_hw_init(MachineState *machine)
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ResetData *reset_info;
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DeviceState *dev;
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int i;
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AHBPnp *ahb_pnp;
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APBPnp *apb_pnp;
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/* Init CPU */
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cpu = SPARC_CPU(cpu_create(machine->cpu_type));
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@ -200,6 +206,20 @@ static void leon3_generic_hw_init(MachineState *machine)
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reset_info->sp = LEON3_RAM_OFFSET + ram_size;
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qemu_register_reset(main_cpu_reset, reset_info);
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ahb_pnp = GRLIB_AHB_PNP(object_new(TYPE_GRLIB_AHB_PNP));
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object_property_set_bool(OBJECT(ahb_pnp), true, "realized", &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(ahb_pnp), 0, LEON3_AHB_PNP_OFFSET);
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grlib_ahb_pnp_add_entry(ahb_pnp, 0, 0, GRLIB_VENDOR_GAISLER,
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GRLIB_LEON3_DEV, GRLIB_AHB_MASTER,
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GRLIB_CPU_AREA);
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apb_pnp = GRLIB_APB_PNP(object_new(TYPE_GRLIB_APB_PNP));
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object_property_set_bool(OBJECT(apb_pnp), true, "realized", &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(apb_pnp), 0, LEON3_APB_PNP_OFFSET);
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grlib_ahb_pnp_add_entry(ahb_pnp, LEON3_APB_PNP_OFFSET, 0xFFF,
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GRLIB_VENDOR_GAISLER, GRLIB_APBMST_DEV,
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GRLIB_AHB_SLAVE, GRLIB_AHBMEM_AREA);
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/* Allocate IRQ manager */
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dev = qdev_create(NULL, TYPE_GRLIB_IRQMP);
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qdev_prop_set_ptr(dev, "set_pil_in", leon3_set_pil_in);
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@ -209,6 +229,9 @@ static void leon3_generic_hw_init(MachineState *machine)
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env->irq_manager = dev;
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env->qemu_irq_ack = leon3_irq_manager;
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cpu_irqs = qemu_allocate_irqs(grlib_irqmp_set_irq, dev, MAX_PILS);
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grlib_apb_pnp_add_entry(apb_pnp, LEON3_IRQMP_OFFSET, 0xFFF,
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GRLIB_VENDOR_GAISLER, GRLIB_IRQMP_DEV,
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2, 0, GRLIB_APBIO_AREA);
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/* Allocate RAM */
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if (ram_size > 1 * GiB) {
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@ -303,6 +326,10 @@ static void leon3_generic_hw_init(MachineState *machine)
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cpu_irqs[LEON3_TIMER_IRQ + i]);
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}
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grlib_apb_pnp_add_entry(apb_pnp, LEON3_TIMER_OFFSET, 0xFFF,
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GRLIB_VENDOR_GAISLER, GRLIB_GPTIMER_DEV,
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0, LEON3_TIMER_IRQ, GRLIB_APBIO_AREA);
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/* Allocate uart */
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if (serial_hd(0)) {
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dev = qdev_create(NULL, TYPE_GRLIB_APB_UART);
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@ -310,6 +337,9 @@ static void leon3_generic_hw_init(MachineState *machine)
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qdev_init_nofail(dev);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_UART_OFFSET);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irqs[LEON3_UART_IRQ]);
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grlib_apb_pnp_add_entry(apb_pnp, LEON3_UART_OFFSET, 0xFFF,
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GRLIB_VENDOR_GAISLER, GRLIB_APBUART_DEV, 1,
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LEON3_UART_IRQ, GRLIB_APBIO_AREA);
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}
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}
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@ -0,0 +1,60 @@
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/*
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* GRLIB AHB APB PNP
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*
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* Copyright (C) 2019 AdaCore
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*
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* Developed by :
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* Frederic Konrad <frederic.konrad@adacore.com>
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 2 of the License, or
|
||||
* (at your option) any later version.
|
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*
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||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#ifndef GRLIB_AHB_APB_PNP_H
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#define GRLIB_AHB_APB_PNP_H
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#define TYPE_GRLIB_AHB_PNP "grlib,ahbpnp"
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#define GRLIB_AHB_PNP(obj) \
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OBJECT_CHECK(AHBPnp, (obj), TYPE_GRLIB_AHB_PNP)
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typedef struct AHBPnp AHBPnp;
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#define TYPE_GRLIB_APB_PNP "grlib,apbpnp"
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#define GRLIB_APB_PNP(obj) \
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OBJECT_CHECK(APBPnp, (obj), TYPE_GRLIB_APB_PNP)
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typedef struct APBPnp APBPnp;
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|
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void grlib_ahb_pnp_add_entry(AHBPnp *dev, uint32_t address, uint32_t mask,
|
||||
uint8_t vendor, uint16_t device, int slave,
|
||||
int type);
|
||||
void grlib_apb_pnp_add_entry(APBPnp *dev, uint32_t address, uint32_t mask,
|
||||
uint8_t vendor, uint16_t device, uint8_t version,
|
||||
uint8_t irq, int type);
|
||||
|
||||
/* VENDORS */
|
||||
#define GRLIB_VENDOR_GAISLER (0x01)
|
||||
/* DEVICES */
|
||||
#define GRLIB_LEON3_DEV (0x03)
|
||||
#define GRLIB_APBMST_DEV (0x06)
|
||||
#define GRLIB_APBUART_DEV (0x0C)
|
||||
#define GRLIB_IRQMP_DEV (0x0D)
|
||||
#define GRLIB_GPTIMER_DEV (0x11)
|
||||
/* TYPE */
|
||||
#define GRLIB_CPU_AREA (0x00)
|
||||
#define GRLIB_APBIO_AREA (0x01)
|
||||
#define GRLIB_AHBMEM_AREA (0x02)
|
||||
|
||||
#define GRLIB_AHB_MASTER (0x00)
|
||||
#define GRLIB_AHB_SLAVE (0x01)
|
||||
|
||||
#endif /* GRLIB_AHB_APB_PNP_H */
|
||||
Loading…
Reference in New Issue