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target/mips: Add fields for SAARI and SAAR CP0 registers 

Add fields for SAARI and SAAR CP0 registers.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
master
Yongbok Kim 2019-01-03 14:12:48 +01:00 committed by Aleksandar Markovic
parent 46d7642fcc
commit 167db30e98
2 changed files with 12 additions and 4 deletions
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10
target/mips/cpu.h
View File

@ -164,8 +164,8 @@ typedef struct mips_def_t mips_def_t;
* 3 BadInstrX
* 4 GuestCtl1 GuestCtl0Ext
* 5 GuestCtl2
* 6 GuestCtl3
* 7
* 6 SAARI GuestCtl3
* 7 SAAR
*
*
* Register 12 Register 13 Register 14 Register 15
@ -546,6 +546,12 @@ struct CPUMIPSState {
* CP0 Register 9
*/
int32_t CP0_Count;
uint32_t CP0_SAARI;
#define CP0SAARI_TARGET 0 /* 5..0 */
uint64_t CP0_SAAR[2];
#define CP0SAAR_BASE 12 /* 43..12 */
#define CP0SAAR_SIZE 1 /* 5..1 */
#define CP0SAAR_EN 0
/*
* CP0 Register 10
*/

6
target/mips/machine.c
View File

@ -214,8 +214,8 @@ const VMStateDescription vmstate_tlb = {
const VMStateDescription vmstate_mips_cpu = {
.name = "cpu",
.version_id = 15,
.minimum_version_id = 15,
.version_id = 16,
.minimum_version_id = 16,
.post_load = cpu_post_load,
.fields = (VMStateField[]) {
/* Active TC */
@ -274,6 +274,8 @@ const VMStateDescription vmstate_mips_cpu = {
VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU),
VMSTATE_INT32(env.CP0_Count, MIPSCPU),
VMSTATE_UINT32(env.CP0_SAARI, MIPSCPU),
VMSTATE_UINT64_ARRAY(env.CP0_SAAR, MIPSCPU, 2),
VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
VMSTATE_INT32(env.CP0_Status, MIPSCPU),