mirror of https://github.com/proxmox/mirror_qemu
target/mips: Add fields for SAARI and SAAR CP0 registers
Add fields for SAARI and SAAR CP0 registers. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>master
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46d7642fcc
commit
167db30e98
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@ -164,8 +164,8 @@ typedef struct mips_def_t mips_def_t;
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* 3 BadInstrX
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* 3 BadInstrX
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* 4 GuestCtl1 GuestCtl0Ext
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* 4 GuestCtl1 GuestCtl0Ext
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* 5 GuestCtl2
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* 5 GuestCtl2
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* 6 GuestCtl3
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* 6 SAARI GuestCtl3
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* 7
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* 7 SAAR
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*
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*
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*
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*
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* Register 12 Register 13 Register 14 Register 15
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* Register 12 Register 13 Register 14 Register 15
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@ -546,6 +546,12 @@ struct CPUMIPSState {
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* CP0 Register 9
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* CP0 Register 9
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*/
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*/
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int32_t CP0_Count;
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int32_t CP0_Count;
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uint32_t CP0_SAARI;
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#define CP0SAARI_TARGET 0 /* 5..0 */
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uint64_t CP0_SAAR[2];
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#define CP0SAAR_BASE 12 /* 43..12 */
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#define CP0SAAR_SIZE 1 /* 5..1 */
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#define CP0SAAR_EN 0
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/*
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/*
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* CP0 Register 10
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* CP0 Register 10
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*/
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*/
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@ -214,8 +214,8 @@ const VMStateDescription vmstate_tlb = {
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const VMStateDescription vmstate_mips_cpu = {
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const VMStateDescription vmstate_mips_cpu = {
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.name = "cpu",
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.name = "cpu",
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.version_id = 15,
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.version_id = 16,
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.minimum_version_id = 15,
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.minimum_version_id = 16,
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.post_load = cpu_post_load,
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.post_load = cpu_post_load,
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.fields = (VMStateField[]) {
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.fields = (VMStateField[]) {
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/* Active TC */
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/* Active TC */
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@ -274,6 +274,8 @@ const VMStateDescription vmstate_mips_cpu = {
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VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
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VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
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VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU),
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VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU),
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VMSTATE_INT32(env.CP0_Count, MIPSCPU),
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VMSTATE_INT32(env.CP0_Count, MIPSCPU),
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VMSTATE_UINT32(env.CP0_SAARI, MIPSCPU),
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VMSTATE_UINT64_ARRAY(env.CP0_SAAR, MIPSCPU, 2),
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VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
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VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
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VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
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VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
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VMSTATE_INT32(env.CP0_Status, MIPSCPU),
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VMSTATE_INT32(env.CP0_Status, MIPSCPU),
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