mirror of https://github.com/proxmox/mirror_qemu
arm-devs queue
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABCAAGBQJR5BsIAAoJEDwlJe0UNgzemaIP/1XIep/THEP6D3X96uJ21u3y 8aVGlkkZMwPSmLm9kN6EuU8C4dwxRIVI/0QewUySdsQApiWUdes+ypeMdckgnyzi j/DxiGpFlqs3U4y778ELHGv7//8Mmfy1vkBY35q3tFS8+DXIwe78Dryvd+uhFb4W X2m0rKME145RQBiG59/P2aEYj3VTJbyjRPye0U97k7LuP3I4uW4HFxM5H6pJce8O /Mb4Llqtigx+MZPrI4oFrZMpHIVmn6o4VHK3TpF0vpXZGng9x5qrB9VgPwDV2O1P eW/RKVZFZgL91y8xSZUS1jQKzqQfJz9CjdNp+md+t14X4bRbaAZC5nNQPM7lT7nM xroOgEWeISRKekulhpNxE9lVI1mRo9BBPLQR1MsdQMEqMZrnGVmJaaUHAclbJVec YIdP2QZ+Q2WLgiz+nKlGnvQxlNEJA+0g1fGL0VHbG1J1eo6MmCbAvq/IEklH0b0y a0yj7yAdvmdco7Xp6bC/lPtnyS5hoFYXu3aLrCsfR/NL93P7FAP9DlL7P3hlGOMB mHqchMP8IDtp/fquH0AAO0D0Uh6imXR6rGDwm8yo0vud2032pIcEYNhD+J+ot7DA I/zL9l5r8FAg0mhzKblIWM7itV5+TXZDJ/T3ThzlhalzhNCrby/SAfmnQ/hpj+sM ctqNJZLG7aay+HPCStPk =c35i -----END PGP SIGNATURE----- Merge remote-tracking branch 'pmaydell/tags/pull-arm-devs-20130715' into staging arm-devs queue # gpg: Signature made Mon 15 Jul 2013 10:53:44 AM CDT using RSA key ID 14360CDE # gpg: Can't check signature: public key not found # By Peter Maydell (4) and others # Via Peter Maydell * pmaydell/tags/pull-arm-devs-20130715: ARM/highbank: add support for Calxeda ECX-2000 / Midway ARM/highbank: prepare for adding similar machines hw/arm/vexpress: Add alias for flash at address 0 on A15 board hw/dma/omap_dma: Fix bugs with DMA requests above 32 sd/pl181.c: Avoid undefined shift behaviour in RWORD macro hw/cpu/a15mpcore: Correct default value for num-irq char/cadence_uart: Fix reset for unattached instances Message-id: 1373904095-27592-1-git-send-email-peter.maydell@linaro.org Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>master
commit
1750d019ce
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@ -183,20 +183,25 @@ type_init(highbank_regs_register_types)
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static struct arm_boot_info highbank_binfo;
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enum cxmachines {
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CALXEDA_HIGHBANK,
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CALXEDA_MIDWAY,
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};
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/* ram_size must be set to match the upper bound of memory in the
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* device tree (linux/arch/arm/boot/dts/highbank.dts), which is
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* normally 0xff900000 or -m 4089. When running this board on a
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* 32-bit host, set the reg value of memory to 0xf7ff00000 in the
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* device tree and pass -m 2047 to QEMU.
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*/
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static void highbank_init(QEMUMachineInitArgs *args)
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static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine)
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{
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ram_addr_t ram_size = args->ram_size;
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const char *cpu_model = args->cpu_model;
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const char *kernel_filename = args->kernel_filename;
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const char *kernel_cmdline = args->kernel_cmdline;
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const char *initrd_filename = args->initrd_filename;
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DeviceState *dev;
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DeviceState *dev = NULL;
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SysBusDevice *busdev;
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qemu_irq *irqp;
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qemu_irq pic[128];
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@ -208,7 +213,14 @@ static void highbank_init(QEMUMachineInitArgs *args)
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char *sysboot_filename;
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if (!cpu_model) {
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cpu_model = "cortex-a9";
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switch (machine) {
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case CALXEDA_HIGHBANK:
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cpu_model = "cortex-a9";
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break;
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case CALXEDA_MIDWAY:
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cpu_model = "cortex-a15";
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break;
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}
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}
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for (n = 0; n < smp_cpus; n++) {
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@ -246,7 +258,19 @@ static void highbank_init(QEMUMachineInitArgs *args)
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}
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}
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dev = qdev_create(NULL, "a9mpcore_priv");
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switch (machine) {
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case CALXEDA_HIGHBANK:
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dev = qdev_create(NULL, "l2x0");
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qdev_init_nofail(dev);
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, 0xfff12000);
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dev = qdev_create(NULL, "a9mpcore_priv");
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break;
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case CALXEDA_MIDWAY:
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dev = qdev_create(NULL, "a15mpcore_priv");
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break;
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}
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qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
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qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
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qdev_init_nofail(dev);
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@ -260,11 +284,6 @@ static void highbank_init(QEMUMachineInitArgs *args)
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pic[n] = qdev_get_gpio_in(dev, n);
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}
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dev = qdev_create(NULL, "l2x0");
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qdev_init_nofail(dev);
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, 0xfff12000);
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dev = qdev_create(NULL, "sp804");
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qdev_prop_set_uint32(dev, "freq0", 150000000);
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qdev_prop_set_uint32(dev, "freq1", 150000000);
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@ -324,6 +343,16 @@ static void highbank_init(QEMUMachineInitArgs *args)
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arm_load_kernel(ARM_CPU(first_cpu), &highbank_binfo);
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}
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static void highbank_init(QEMUMachineInitArgs *args)
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{
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calxeda_init(args, CALXEDA_HIGHBANK);
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}
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static void midway_init(QEMUMachineInitArgs *args)
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{
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calxeda_init(args, CALXEDA_MIDWAY);
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}
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static QEMUMachine highbank_machine = {
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.name = "highbank",
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.desc = "Calxeda Highbank (ECX-1000)",
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@ -333,9 +362,19 @@ static QEMUMachine highbank_machine = {
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DEFAULT_MACHINE_OPTIONS,
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};
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static void highbank_machine_init(void)
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static QEMUMachine midway_machine = {
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.name = "midway",
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.desc = "Calxeda Midway (ECX-2000)",
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.init = midway_init,
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.block_default_type = IF_SCSI,
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.max_cpus = 4,
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DEFAULT_MACHINE_OPTIONS,
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};
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static void calxeda_machines_init(void)
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{
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qemu_register_machine(&highbank_machine);
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qemu_register_machine(&midway_machine);
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}
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machine_init(highbank_machine_init);
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machine_init(calxeda_machines_init);
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@ -67,6 +67,7 @@ enum {
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VE_CLCD,
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VE_NORFLASH0,
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VE_NORFLASH1,
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VE_NORFLASHALIAS,
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VE_SRAM,
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VE_VIDEORAM,
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VE_ETHERNET,
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@ -104,9 +105,11 @@ static hwaddr motherboard_legacy_map[] = {
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[VE_VIDEORAM] = 0x4c000000,
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[VE_ETHERNET] = 0x4e000000,
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[VE_USB] = 0x4f000000,
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[VE_NORFLASHALIAS] = -1, /* not present */
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};
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static hwaddr motherboard_aseries_map[] = {
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[VE_NORFLASHALIAS] = 0,
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/* CS0: 0x08000000 .. 0x0c000000 */
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[VE_NORFLASH0] = 0x08000000,
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/* CS4: 0x0c000000 .. 0x10000000 */
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@ -400,10 +403,13 @@ static void vexpress_common_init(const VEDBoardInfo *daughterboard,
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qemu_irq pic[64];
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uint32_t sys_id;
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DriveInfo *dinfo;
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pflash_t *pflash0;
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ram_addr_t vram_size, sram_size;
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MemoryRegion *sysmem = get_system_memory();
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MemoryRegion *vram = g_new(MemoryRegion, 1);
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MemoryRegion *sram = g_new(MemoryRegion, 1);
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MemoryRegion *flashalias = g_new(MemoryRegion, 1);
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MemoryRegion *flash0mem;
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const hwaddr *map = daughterboard->motherboard_map;
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int i;
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@ -471,15 +477,24 @@ static void vexpress_common_init(const VEDBoardInfo *daughterboard,
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sysbus_create_simple("pl111", map[VE_CLCD], pic[14]);
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dinfo = drive_get_next(IF_PFLASH);
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if (!pflash_cfi01_register(map[VE_NORFLASH0], NULL, "vexpress.flash0",
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pflash0 = pflash_cfi01_register(map[VE_NORFLASH0], NULL, "vexpress.flash0",
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VEXPRESS_FLASH_SIZE, dinfo ? dinfo->bdrv : NULL,
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VEXPRESS_FLASH_SECT_SIZE,
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VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE, 4,
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0x00, 0x89, 0x00, 0x18, 0)) {
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0x00, 0x89, 0x00, 0x18, 0);
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if (!pflash0) {
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fprintf(stderr, "vexpress: error registering flash 0.\n");
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exit(1);
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}
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if (map[VE_NORFLASHALIAS] != -1) {
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/* Map flash 0 as an alias into low memory */
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flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0);
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memory_region_init_alias(flashalias, NULL, "vexpress.flashalias",
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flash0mem, 0, VEXPRESS_FLASH_SIZE);
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memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias);
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}
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dinfo = drive_get_next(IF_PFLASH);
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if (!pflash_cfi01_register(map[VE_NORFLASH1], NULL, "vexpress.flash1",
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VEXPRESS_FLASH_SIZE, dinfo ? dinfo->bdrv : NULL,
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@ -157,7 +157,9 @@ static void uart_rx_reset(UartState *s)
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{
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s->rx_wpos = 0;
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s->rx_count = 0;
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qemu_chr_accept_input(s->chr);
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if (s->chr) {
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qemu_chr_accept_input(s->chr);
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}
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s->r[R_SR] |= UART_SR_INTR_REMPTY;
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s->r[R_SR] &= ~UART_SR_INTR_RFUL;
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@ -82,12 +82,12 @@ static int a15mp_priv_init(SysBusDevice *dev)
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static Property a15mp_priv_properties[] = {
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DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1),
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/* The Cortex-A15MP may have anything from 0 to 224 external interrupt
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* IRQ lines (with another 32 internal). We default to 64+32, which
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* IRQ lines (with another 32 internal). We default to 128+32, which
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* is the number provided by the Cortex-A15MP test chip in the
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* Versatile Express A15 development board.
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* Other boards may differ and should set this property appropriately.
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*/
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DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 96),
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DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 160),
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DEFINE_PROP_END_OF_LIST(),
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};
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@ -248,7 +248,7 @@ static void omap_dma_deactivate_channel(struct omap_dma_s *s,
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/* Don't deactive the channel if it is synchronized and the DMA request is
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active */
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if (ch->sync && ch->enable && (s->dma->drqbmp & (1 << ch->sync)))
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if (ch->sync && ch->enable && (s->dma->drqbmp & (1ULL << ch->sync)))
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return;
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if (ch->active) {
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/* TODO: theoretically if ch->sync && ch->prefetch &&
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* !s->dma->drqbmp[ch->sync], we should also activate and fetch
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* from source and then stall until signalled. */
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if ((!ch->sync) || (s->dma->drqbmp & (1 << ch->sync)))
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if ((!ch->sync) || (s->dma->drqbmp & (1ULL << ch->sync))) {
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omap_dma_activate_channel(s, ch);
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}
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}
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}
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struct omap_dma_s *s = (struct omap_dma_s *) opaque;
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/* The request pins are level triggered in QEMU. */
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if (req) {
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if (~s->dma->drqbmp & (1 << drq)) {
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s->dma->drqbmp |= 1 << drq;
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if (~s->dma->drqbmp & (1ULL << drq)) {
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s->dma->drqbmp |= 1ULL << drq;
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omap_dma_process_request(s, drq);
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}
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} else
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s->dma->drqbmp &= ~(1 << drq);
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s->dma->drqbmp &= ~(1ULL << drq);
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}
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/* XXX: this won't be needed once soc_dma knows about clocks. */
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@ -175,7 +175,7 @@ static void pl181_send_command(pl181_state *s)
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if (rlen < 0)
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goto error;
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if (s->cmd & PL181_CMD_RESPONSE) {
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#define RWORD(n) ((response[n] << 24) | (response[n + 1] << 16) \
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#define RWORD(n) (((uint32_t)response[n] << 24) | (response[n + 1] << 16) \
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| (response[n + 2] << 8) | response[n + 3])
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if (rlen == 0 || (rlen == 4 && (s->cmd & PL181_CMD_LONGRESP)))
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goto error;
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