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include/qemu: Add TCGCPUOps typedef to typedefs.h 

QEMU coding style recommends using structure typedefs.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
master
Richard Henderson 2024-01-28 12:46:44 +10:00
parent 93c6091bfa
commit 1764ad70ce
26 changed files with 29 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
bsd-user/signal.c
View File

@ -1022,7 +1022,7 @@ void process_pending_signals(CPUArchState *env)
void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
MMUAccessType access_type, bool maperr, uintptr_t ra)
{
const struct TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops;
const TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops;
if (tcg_ops->record_sigsegv) {
tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra);
@ -1038,7 +1038,7 @@ void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr,
MMUAccessType access_type, uintptr_t ra)
{
const struct TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops;
const TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops;
if (tcg_ops->record_sigbus) {
tcg_ops->record_sigbus(cpu, addr, access_type, ra);

5
include/hw/core/cpu.h
View File

@ -90,9 +90,6 @@ typedef enum MMUAccessType {
typedef struct CPUWatchpoint CPUWatchpoint;
/* see tcg-cpu-ops.h */
struct TCGCPUOps;
/* see accel-cpu.h */
struct AccelCPUClass;
@ -177,7 +174,7 @@ struct CPUClass {
const struct SysemuCPUOps *sysemu_ops;
/* when TCG is not available, this pointer is NULL */
const struct TCGCPUOps *tcg_ops;
const TCGCPUOps *tcg_ops;
/*
* if not NULL, this is called in order for the CPUClass to initialize

1
include/qemu/typedefs.h
View File

@ -131,6 +131,7 @@ typedef struct Range Range;
typedef struct ReservedRegion ReservedRegion;
typedef struct SHPCDevice SHPCDevice;
typedef struct SSIBus SSIBus;
typedef struct TCGCPUOps TCGCPUOps;
typedef struct TCGHelperInfo TCGHelperInfo;
typedef struct TranslationBlock TranslationBlock;
typedef struct VirtIODevice VirtIODevice;

4
linux-user/signal.c
View File

@ -671,7 +671,7 @@ void force_sigsegv(int oldsig)
void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
MMUAccessType access_type, bool maperr, uintptr_t ra)
{
const struct TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops;
const TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops;
if (tcg_ops->record_sigsegv) {
tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra);
@ -687,7 +687,7 @@ void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr,
MMUAccessType access_type, uintptr_t ra)
{
const struct TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops;
const TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops;
if (tcg_ops->record_sigbus) {
tcg_ops->record_sigbus(cpu, addr, access_type, ra);

2
target/alpha/cpu.c
View File

@ -203,7 +203,7 @@ static const struct SysemuCPUOps alpha_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
static const struct TCGCPUOps alpha_tcg_ops = {
static const TCGCPUOps alpha_tcg_ops = {
.initialize = alpha_translate_init,
.restore_state_to_opc = alpha_restore_state_to_opc,

2
target/arm/cpu.c
View File

@ -2458,7 +2458,7 @@ static const struct SysemuCPUOps arm_sysemu_ops = {
#endif
#ifdef CONFIG_TCG
static const struct TCGCPUOps arm_tcg_ops = {
static const TCGCPUOps arm_tcg_ops = {
.initialize = arm_translate_init,
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
.debug_excp_handler = arm_debug_excp_handler,

2
target/arm/tcg/cpu32.c
View File

@ -1018,7 +1018,7 @@ static void pxa270c5_initfn(Object *obj)
cpu->reset_sctlr = 0x00000078;
}
static const struct TCGCPUOps arm_v7m_tcg_ops = {
static const TCGCPUOps arm_v7m_tcg_ops = {
.initialize = arm_translate_init,
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
.debug_excp_handler = arm_debug_excp_handler,

2
target/avr/cpu.c
View File

@ -210,7 +210,7 @@ static const struct SysemuCPUOps avr_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
static const struct TCGCPUOps avr_tcg_ops = {
static const TCGCPUOps avr_tcg_ops = {
.initialize = avr_cpu_tcg_init,
.synchronize_from_tb = avr_cpu_synchronize_from_tb,
.restore_state_to_opc = avr_restore_state_to_opc,

4
target/cris/cpu.c
View File

@ -178,7 +178,7 @@ static const struct SysemuCPUOps cris_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
static const struct TCGCPUOps crisv10_tcg_ops = {
static const TCGCPUOps crisv10_tcg_ops = {
.initialize = cris_initialize_crisv10_tcg,
.restore_state_to_opc = cris_restore_state_to_opc,
@ -189,7 +189,7 @@ static const struct TCGCPUOps crisv10_tcg_ops = {
#endif /* !CONFIG_USER_ONLY */
};
static const struct TCGCPUOps crisv32_tcg_ops = {
static const TCGCPUOps crisv32_tcg_ops = {
.initialize = cris_initialize_tcg,
.restore_state_to_opc = cris_restore_state_to_opc,

2
target/hexagon/cpu.c
View File

@ -337,7 +337,7 @@ static void hexagon_cpu_init(Object *obj)
#include "hw/core/tcg-cpu-ops.h"
static const struct TCGCPUOps hexagon_tcg_ops = {
static const TCGCPUOps hexagon_tcg_ops = {
.initialize = hexagon_translate_init,
.synchronize_from_tb = hexagon_cpu_synchronize_from_tb,
.restore_state_to_opc = hexagon_restore_state_to_opc,

2
target/hppa/cpu.c
View File

@ -170,7 +170,7 @@ static const struct SysemuCPUOps hppa_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
static const struct TCGCPUOps hppa_tcg_ops = {
static const TCGCPUOps hppa_tcg_ops = {
.initialize = hppa_translate_init,
.synchronize_from_tb = hppa_cpu_synchronize_from_tb,
.restore_state_to_opc = hppa_restore_state_to_opc,

2
target/i386/tcg/tcg-cpu.c
View File

@ -106,7 +106,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs)
#include "hw/core/tcg-cpu-ops.h"
static const struct TCGCPUOps x86_tcg_ops = {
static const TCGCPUOps x86_tcg_ops = {
.initialize = tcg_x86_init,
.synchronize_from_tb = x86_cpu_synchronize_from_tb,
.restore_state_to_opc = x86_restore_state_to_opc,

2
target/loongarch/cpu.c
View File

@ -734,7 +734,7 @@ void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps loongarch_tcg_ops = {
static TCGCPUOps loongarch_tcg_ops = {
.initialize = loongarch_translate_init,
.synchronize_from_tb = loongarch_cpu_synchronize_from_tb,
.restore_state_to_opc = loongarch_restore_state_to_opc,

2
target/m68k/cpu.c
View File

@ -525,7 +525,7 @@ static const struct SysemuCPUOps m68k_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
static const struct TCGCPUOps m68k_tcg_ops = {
static const TCGCPUOps m68k_tcg_ops = {
.initialize = m68k_tcg_init,
.restore_state_to_opc = m68k_restore_state_to_opc,

2
target/microblaze/cpu.c
View File

@ -387,7 +387,7 @@ static const struct SysemuCPUOps mb_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
static const struct TCGCPUOps mb_tcg_ops = {
static const TCGCPUOps mb_tcg_ops = {
.initialize = mb_tcg_init,
.synchronize_from_tb = mb_cpu_synchronize_from_tb,
.restore_state_to_opc = mb_restore_state_to_opc,

2
target/mips/cpu.c
View File

@ -549,7 +549,7 @@ static const struct SysemuCPUOps mips_sysemu_ops = {
* NB: cannot be const, as some elements are changed for specific
* mips hardware (see hw/mips/jazz.c).
*/
static const struct TCGCPUOps mips_tcg_ops = {
static const TCGCPUOps mips_tcg_ops = {
.initialize = mips_tcg_init,
.synchronize_from_tb = mips_cpu_synchronize_from_tb,
.restore_state_to_opc = mips_restore_state_to_opc,

2
target/nios2/cpu.c
View File

@ -354,7 +354,7 @@ static const struct SysemuCPUOps nios2_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
static const struct TCGCPUOps nios2_tcg_ops = {
static const TCGCPUOps nios2_tcg_ops = {
.initialize = nios2_tcg_init,
.restore_state_to_opc = nios2_restore_state_to_opc,

2
target/openrisc/cpu.c
View File

@ -213,7 +213,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
static const struct TCGCPUOps openrisc_tcg_ops = {
static const TCGCPUOps openrisc_tcg_ops = {
.initialize = openrisc_translate_init,
.synchronize_from_tb = openrisc_cpu_synchronize_from_tb,
.restore_state_to_opc = openrisc_restore_state_to_opc,

2
target/ppc/cpu_init.c
View File

@ -7332,7 +7332,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops = {
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
static const struct TCGCPUOps ppc_tcg_ops = {
static const TCGCPUOps ppc_tcg_ops = {
.initialize = ppc_translate_init,
.restore_state_to_opc = ppc_restore_state_to_opc,

2
target/riscv/tcg/tcg-cpu.c
View File

@ -129,7 +129,7 @@ static void riscv_restore_state_to_opc(CPUState *cs,
env->bins = data[1];
}
static const struct TCGCPUOps riscv_tcg_ops = {
static const TCGCPUOps riscv_tcg_ops = {
.initialize = riscv_translate_init,
.synchronize_from_tb = riscv_cpu_synchronize_from_tb,
.restore_state_to_opc = riscv_restore_state_to_opc,

2
target/rx/cpu.c
View File

@ -178,7 +178,7 @@ static const struct SysemuCPUOps rx_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
static const struct TCGCPUOps rx_tcg_ops = {
static const TCGCPUOps rx_tcg_ops = {
.initialize = rx_translate_init,
.synchronize_from_tb = rx_cpu_synchronize_from_tb,
.restore_state_to_opc = rx_restore_state_to_opc,

2
target/s390x/cpu.c
View File

@ -319,7 +319,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
static const struct TCGCPUOps s390_tcg_ops = {
static const TCGCPUOps s390_tcg_ops = {
.initialize = s390x_translate_init,
.restore_state_to_opc = s390x_restore_state_to_opc,

2
target/sh4/cpu.c
View File

@ -237,7 +237,7 @@ static const struct SysemuCPUOps sh4_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
static const struct TCGCPUOps superh_tcg_ops = {
static const TCGCPUOps superh_tcg_ops = {
.initialize = sh4_translate_init,
.synchronize_from_tb = superh_cpu_synchronize_from_tb,
.restore_state_to_opc = superh_restore_state_to_opc,

2
target/sparc/cpu.c
View File

@ -874,7 +874,7 @@ static const struct SysemuCPUOps sparc_sysemu_ops = {
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
static const struct TCGCPUOps sparc_tcg_ops = {
static const TCGCPUOps sparc_tcg_ops = {
.initialize = sparc_tcg_init,
.synchronize_from_tb = sparc_cpu_synchronize_from_tb,
.restore_state_to_opc = sparc_restore_state_to_opc,

2
target/tricore/cpu.c
View File

@ -173,7 +173,7 @@ static const struct SysemuCPUOps tricore_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
static const struct TCGCPUOps tricore_tcg_ops = {
static const TCGCPUOps tricore_tcg_ops = {
.initialize = tricore_tcg_init,
.synchronize_from_tb = tricore_cpu_synchronize_from_tb,
.restore_state_to_opc = tricore_restore_state_to_opc,

2
target/xtensa/cpu.c
View File

@ -222,7 +222,7 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = {
#include "hw/core/tcg-cpu-ops.h"
static const struct TCGCPUOps xtensa_tcg_ops = {
static const TCGCPUOps xtensa_tcg_ops = {
.initialize = xtensa_translate_init,
.debug_excp_handler = xtensa_breakpoint_handler,
.restore_state_to_opc = xtensa_restore_state_to_opc,