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Clean-ups: qom-ify serial and remove QDEV_PROP_PTR 

Hi,
 
 QDEV_PROP_PTR is marked in multiple places as "FIXME/TODO/remove
 me". In most cases, it can be easily replaced with QDEV_PROP_LINK when
 the pointer points to an Object.
 
 There are a few places where such substitution isn't possible. For
 those places, it seems reasonable to use a specific setter method
 instead, and keep the user_creatable = false. In other places,
 proper usage of qdev or other facilies is the solution.
 
 The serial code wasn't converted to qdev, which makes it a bit more
 archaic to deal with. Let's convert it first, so we can more easily
 embed it from other devices, and re-export some properties and drop
 QDEV_PROP_PTR usage.
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Merge remote-tracking branch 'remotes/elmarco/tags/prop-ptr-pull-request' into staging

Clean-ups: qom-ify serial and remove QDEV_PROP_PTR

Hi,

QDEV_PROP_PTR is marked in multiple places as "FIXME/TODO/remove
me". In most cases, it can be easily replaced with QDEV_PROP_LINK when
the pointer points to an Object.

There are a few places where such substitution isn't possible. For
those places, it seems reasonable to use a specific setter method
instead, and keep the user_creatable = false. In other places,
proper usage of qdev or other facilies is the solution.

The serial code wasn't converted to qdev, which makes it a bit more
archaic to deal with. Let's convert it first, so we can more easily
embed it from other devices, and re-export some properties and drop
QDEV_PROP_PTR usage.

# gpg: Signature made Tue 07 Jan 2020 15:01:26 GMT
# gpg:                using RSA key 87A9BD933F87C606D276F62DDAE8E10975969CE5
# gpg:                issuer "marcandre.lureau@redhat.com"
# gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" [full]
# gpg:                 aka "Marc-André Lureau <marcandre.lureau@gmail.com>" [full]
# Primary key fingerprint: 87A9 BD93 3F87 C606 D276  F62D DAE8 E109 7596 9CE5

* remotes/elmarco/tags/prop-ptr-pull-request: (37 commits)
  qdev/qom: remove some TODO limitations now that PROP_PTR is gone
  qdev: remove QDEV_PROP_PTR
  qdev: remove PROP_MEMORY_REGION
  omap-gpio: remove PROP_PTR
  omap-i2c: remove PROP_PTR
  omap-intc: remove PROP_PTR
  smbus-eeprom: remove PROP_PTR
  cris: improve passing PIC interrupt vector to the CPU
  mips/cps: fix setting saar property
  qdev: use g_strcmp0() instead of open-coding it
  leon3: use qdev gpio facilities for the PIL
  leon3: use qemu_irq framework instead of callback as property
  dp8393x: replace PROP_PTR with PROP_LINK
  etraxfs: remove PROP_PTR usage
  lance: replace PROP_PTR with PROP_LINK
  vmmouse: replace PROP_PTR with PROP_LINK
  sm501: make SerialMM a child, export chardev property
  mips: use sysbus_mmio_get_region() instead of internal fields
  mips: use sysbus_add_io()
  mips: baudbase is 115200 by default
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
master
Peter Maydell 2020-01-07 17:54:29 +00:00
parent 035eed4c0d f0d753b1c1
commit 1bbd1511b6
47 changed files with 514 additions and 396 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
chardev/char.c
View File

@ -37,6 +37,7 @@
#include "qemu/help_option.h"
#include "qemu/module.h"
#include "qemu/option.h"
#include "qemu/id.h"
#include "chardev/char-mux.h"
@ -944,10 +945,10 @@ void qemu_chr_set_feature(Chardev *chr,
return set_bit(feature, chr->features);
}
Chardev *qemu_chardev_new(const char *id, const char *typename,
ChardevBackend *backend,
GMainContext *gcontext,
Error **errp)
static Chardev *chardev_new(const char *id, const char *typename,
ChardevBackend *backend,
GMainContext *gcontext,
Error **errp)
{
Object *obj;
Chardev *chr = NULL;
@ -991,6 +992,21 @@ end:
return chr;
}
Chardev *qemu_chardev_new(const char *id, const char *typename,
ChardevBackend *backend,
GMainContext *gcontext,
Error **errp)
{
g_autofree char *genid = NULL;
if (!id) {
genid = id_generate(ID_CHR);
id = genid;
}
return chardev_new(id, typename, backend, gcontext, errp);
}
ChardevReturn *qmp_chardev_add(const char *id, ChardevBackend *backend,
Error **errp)
{
@ -1003,8 +1019,8 @@ ChardevReturn *qmp_chardev_add(const char *id, ChardevBackend *backend,
return NULL;
}
chr = qemu_chardev_new(id, object_class_get_name(OBJECT_CLASS(cc)),
backend, NULL, errp);
chr = chardev_new(id, object_class_get_name(OBJECT_CLASS(cc)),
backend, NULL, errp);
if (!chr) {
return NULL;
}
@ -1061,8 +1077,8 @@ ChardevReturn *qmp_chardev_change(const char *id, ChardevBackend *backend,
return NULL;
}
chr_new = qemu_chardev_new(NULL, object_class_get_name(OBJECT_CLASS(cc)),
backend, chr->gcontext, errp);
chr_new = chardev_new(NULL, object_class_get_name(OBJECT_CLASS(cc)),
backend, chr->gcontext, errp);
if (!chr_new) {
return NULL;
}

8
hw/arm/omap1.c
View File

@ -3889,7 +3889,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *dram,
s->ih[0] = qdev_create(NULL, "omap-intc");
qdev_prop_set_uint32(s->ih[0], "size", 0x100);
qdev_prop_set_ptr(s->ih[0], "clk", omap_findclk(s, "arminth_ck"));
omap_intc_set_iclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "arminth_ck"));
qdev_init_nofail(s->ih[0]);
busdev = SYS_BUS_DEVICE(s->ih[0]);
sysbus_connect_irq(busdev, 0,
@ -3899,7 +3899,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *dram,
sysbus_mmio_map(busdev, 0, 0xfffecb00);
s->ih[1] = qdev_create(NULL, "omap-intc");
qdev_prop_set_uint32(s->ih[1], "size", 0x800);
qdev_prop_set_ptr(s->ih[1], "clk", omap_findclk(s, "arminth_ck"));
omap_intc_set_iclk(OMAP_INTC(s->ih[1]), omap_findclk(s, "arminth_ck"));
qdev_init_nofail(s->ih[1]);
busdev = SYS_BUS_DEVICE(s->ih[1]);
sysbus_connect_irq(busdev, 0,
@ -4012,7 +4012,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *dram,
s->gpio = qdev_create(NULL, "omap-gpio");
qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);
qdev_prop_set_ptr(s->gpio, "clk", omap_findclk(s, "arm_gpio_ck"));
omap_gpio_set_clk(OMAP1_GPIO(s->gpio), omap_findclk(s, "arm_gpio_ck"));
qdev_init_nofail(s->gpio);
sysbus_connect_irq(SYS_BUS_DEVICE(s->gpio), 0,
qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1));
@ -4030,7 +4030,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *dram,
s->i2c[0] = qdev_create(NULL, "omap_i2c");
qdev_prop_set_uint8(s->i2c[0], "revision", 0x11);
qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "mpuper_ck"));
omap_i2c_set_fclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "mpuper_ck"));
qdev_init_nofail(s->i2c[0]);
busdev = SYS_BUS_DEVICE(s->i2c[0]);
sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C));

25
hw/arm/omap2.c
View File

@ -2308,8 +2308,8 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram,
/* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
s->ih[0] = qdev_create(NULL, "omap2-intc");
qdev_prop_set_uint8(s->ih[0], "revision", 0x21);
qdev_prop_set_ptr(s->ih[0], "fclk", omap_findclk(s, "mpu_intc_fclk"));
qdev_prop_set_ptr(s->ih[0], "iclk", omap_findclk(s, "mpu_intc_iclk"));
omap_intc_set_fclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "mpu_intc_fclk"));
omap_intc_set_iclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "mpu_intc_iclk"));
qdev_init_nofail(s->ih[0]);
busdev = SYS_BUS_DEVICE(s->ih[0]);
sysbus_connect_irq(busdev, 0,
@ -2425,8 +2425,8 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram,
s->i2c[0] = qdev_create(NULL, "omap_i2c");
qdev_prop_set_uint8(s->i2c[0], "revision", 0x34);
qdev_prop_set_ptr(s->i2c[0], "iclk", omap_findclk(s, "i2c1.iclk"));
qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "i2c1.fclk"));
omap_i2c_set_iclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "i2c1.iclk"));
omap_i2c_set_fclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "i2c1.fclk"));
qdev_init_nofail(s->i2c[0]);
busdev = SYS_BUS_DEVICE(s->i2c[0]);
sysbus_connect_irq(busdev, 0,
@ -2437,8 +2437,8 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram,
s->i2c[1] = qdev_create(NULL, "omap_i2c");
qdev_prop_set_uint8(s->i2c[1], "revision", 0x34);
qdev_prop_set_ptr(s->i2c[1], "iclk", omap_findclk(s, "i2c2.iclk"));
qdev_prop_set_ptr(s->i2c[1], "fclk", omap_findclk(s, "i2c2.fclk"));
omap_i2c_set_iclk(OMAP_I2C(s->i2c[1]), omap_findclk(s, "i2c2.iclk"));
omap_i2c_set_fclk(OMAP_I2C(s->i2c[1]), omap_findclk(s, "i2c2.fclk"));
qdev_init_nofail(s->i2c[1]);
busdev = SYS_BUS_DEVICE(s->i2c[1]);
sysbus_connect_irq(busdev, 0,
@ -2449,13 +2449,14 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram,
s->gpio = qdev_create(NULL, "omap2-gpio");
qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);
qdev_prop_set_ptr(s->gpio, "iclk", omap_findclk(s, "gpio_iclk"));
qdev_prop_set_ptr(s->gpio, "fclk0", omap_findclk(s, "gpio1_dbclk"));
qdev_prop_set_ptr(s->gpio, "fclk1", omap_findclk(s, "gpio2_dbclk"));
qdev_prop_set_ptr(s->gpio, "fclk2", omap_findclk(s, "gpio3_dbclk"));
qdev_prop_set_ptr(s->gpio, "fclk3", omap_findclk(s, "gpio4_dbclk"));
omap2_gpio_set_iclk(OMAP2_GPIO(s->gpio), omap_findclk(s, "gpio_iclk"));
omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 0, omap_findclk(s, "gpio1_dbclk"));
omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 1, omap_findclk(s, "gpio2_dbclk"));
omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 2, omap_findclk(s, "gpio3_dbclk"));
omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 3, omap_findclk(s, "gpio4_dbclk"));
if (s->mpu_model == omap2430) {
qdev_prop_set_ptr(s->gpio, "fclk4", omap_findclk(s, "gpio5_dbclk"));
omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 4,
omap_findclk(s, "gpio5_dbclk"));
}
qdev_init_nofail(s->gpio);
busdev = SYS_BUS_DEVICE(s->gpio);

2
hw/char/omap_uart.c
View File

@ -27,7 +27,7 @@
struct omap_uart_s {
MemoryRegion iomem;
hwaddr base;
SerialState *serial; /* TODO */
SerialMM *serial; /* TODO */
struct omap_target_agent_s *ta;
omap_clk fclk;
qemu_irq irq;

12
hw/char/serial-isa.c
View File

@ -73,9 +73,8 @@ static void serial_isa_realizefn(DeviceState *dev, Error **errp)
}
index++;
s->baudbase = 115200;
isa_init_irq(isadev, &s->irq, isa->isairq);
serial_realize_core(s, errp);
object_property_set_bool(OBJECT(s), true, "realized", errp);
qdev_set_legacy_instance_id(dev, isa->iobase, 3);
memory_region_init_io(&s->io, OBJECT(isa), &serial_io_ops, s, "serial", 8);
@ -111,10 +110,19 @@ static void serial_isa_class_initfn(ObjectClass *klass, void *data)
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
static void serial_isa_initfn(Object *o)
{
ISASerialState *self = ISA_SERIAL(o);
object_initialize_child(o, "serial", &self->state, sizeof(self->state),
TYPE_SERIAL, &error_abort, NULL);
}
static const TypeInfo serial_isa_info = {
.name = TYPE_ISA_SERIAL,
.parent = TYPE_ISA_DEVICE,
.instance_size = sizeof(ISASerialState),
.instance_init = serial_isa_initfn,
.class_init = serial_isa_class_initfn,
};

55
hw/char/serial-pci-multi.c
View File

@ -56,7 +56,7 @@ static void multi_serial_pci_exit(PCIDevice *dev)
for (i = 0; i < pci->ports; i++) {
s = pci->state + i;
serial_exit_core(s);
object_property_set_bool(OBJECT(s), false, "realized", NULL);
memory_region_del_subregion(&pci->iobar, &s->io);
g_free(pci->name[i]);
}
@ -77,43 +77,43 @@ static void multi_serial_irq_mux(void *opaque, int n, int level)
pci_set_irq(&pci->dev, pending);
}
static size_t multi_serial_get_port_count(PCIDeviceClass *pc)
{
switch (pc->device_id) {
case 0x0003:
return 2;
case 0x0004:
return 4;
}
g_assert_not_reached();
}
static void multi_serial_pci_realize(PCIDevice *dev, Error **errp)
{
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
SerialState *s;
Error *err = NULL;
int i, nr_ports = 0;
switch (pc->device_id) {
case 0x0003:
nr_ports = 2;
break;
case 0x0004:
nr_ports = 4;
break;
}
assert(nr_ports > 0);
assert(nr_ports <= PCI_SERIAL_MAX_PORTS);
size_t i, nports = multi_serial_get_port_count(pc);
pci->dev.config[PCI_CLASS_PROG] = pci->prog_if;
pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
memory_region_init(&pci->iobar, OBJECT(pci), "multiserial", 8 * nr_ports);
memory_region_init(&pci->iobar, OBJECT(pci), "multiserial", 8 * nports);
pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->iobar);
pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci,
nr_ports);
pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci, nports);
for (i = 0; i < nr_ports; i++) {
for (i = 0; i < nports; i++) {
s = pci->state + i;
s->baudbase = 115200;
serial_realize_core(s, &err);
object_property_set_bool(OBJECT(s), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
multi_serial_pci_exit(dev);
return;
}
s->irq = pci->irqs[i];
pci->name[i] = g_strdup_printf("uart #%d", i + 1);
pci->name[i] = g_strdup_printf("uart #%zu", i + 1);
memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s,
pci->name[i], 8);
memory_region_add_subregion(&pci->iobar, 8 * i, &s->io);
@ -180,10 +180,24 @@ static void multi_4x_serial_pci_class_initfn(ObjectClass *klass, void *data)
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
static void multi_serial_init(Object *o)
{
PCIDevice *dev = PCI_DEVICE(o);
PCIMultiSerialState *pms = DO_UPCAST(PCIMultiSerialState, dev, dev);
size_t i, nports = multi_serial_get_port_count(PCI_DEVICE_GET_CLASS(dev));
for (i = 0; i < nports; i++) {
object_initialize_child(o, "serial[*]", &pms->state[i],
sizeof(pms->state[i]),
TYPE_SERIAL, &error_abort, NULL);
}
}
static const TypeInfo multi_2x_serial_pci_info = {
.name = "pci-serial-2x",
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PCIMultiSerialState),
.instance_init = multi_serial_init,
.class_init = multi_2x_serial_pci_class_initfn,
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
@ -195,6 +209,7 @@ static const TypeInfo multi_4x_serial_pci_info = {
.name = "pci-serial-4x",
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PCIMultiSerialState),
.instance_init = multi_serial_init,
.class_init = multi_4x_serial_pci_class_initfn,
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },

18
hw/char/serial-pci.c
View File

@ -40,6 +40,8 @@ typedef struct PCISerialState {
uint8_t prog_if;
} PCISerialState;
#define TYPE_PCI_SERIAL "pci-serial"
#define PCI_SERIAL(s) OBJECT_CHECK(PCISerialState, (s), TYPE_PCI_SERIAL)
static void serial_pci_realize(PCIDevice *dev, Error **errp)
{
@ -47,8 +49,7 @@ static void serial_pci_realize(PCIDevice *dev, Error **errp)
SerialState *s = &pci->state;
Error *err = NULL;
s->baudbase = 115200;
serial_realize_core(s, &err);
object_property_set_bool(OBJECT(s), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@ -67,7 +68,7 @@ static void serial_pci_exit(PCIDevice *dev)
PCISerialState *pci = DO_UPCAST(PCISerialState, dev, dev);
SerialState *s = &pci->state;
serial_exit_core(s);
object_property_set_bool(OBJECT(s), false, "realized", NULL);
qemu_free_irq(s->irq);
}
@ -103,10 +104,19 @@ static void serial_pci_class_initfn(ObjectClass *klass, void *data)
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
static void serial_pci_init(Object *o)
{
PCISerialState *ps = PCI_SERIAL(o);
object_initialize_child(o, "serial", &ps->state, sizeof(ps->state),
TYPE_SERIAL, &error_abort, NULL);
}
static const TypeInfo serial_pci_info = {
.name = "pci-serial",
.name = TYPE_PCI_SERIAL,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PCISerialState),
.instance_init = serial_pci_init,
.class_init = serial_pci_class_initfn,
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },

194
hw/char/serial.c
View File

@ -34,6 +34,7 @@
#include "sysemu/runstate.h"
#include "qemu/error-report.h"
#include "trace.h"
#include "hw/qdev-properties.h"
//#define DEBUG_SERIAL
@ -933,8 +934,10 @@ static int serial_be_change(void *opaque)
return 0;
}
void serial_realize_core(SerialState *s, Error **errp)
static void serial_realize(DeviceState *dev, Error **errp)
{
SerialState *s = SERIAL(dev);
s->modem_status_poll = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) serial_update_msl, s);
s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) fifo_timeout_int, s);
@ -947,8 +950,10 @@ void serial_realize_core(SerialState *s, Error **errp)
serial_reset(s);
}
void serial_exit_core(SerialState *s)
static void serial_unrealize(DeviceState *dev, Error **errp)
{
SerialState *s = SERIAL(dev);
qemu_chr_fe_deinit(&s->chr, false);
timer_del(s->modem_status_poll);
@ -980,40 +985,89 @@ const MemoryRegionOps serial_io_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
SerialState *serial_init(int base, qemu_irq irq, int baudbase,
Chardev *chr, MemoryRegion *system_io)
static void serial_io_realize(DeviceState *dev, Error **errp)
{
SerialState *s;
SerialIO *sio = SERIAL_IO(dev);
SerialState *s = &sio->serial;
Error *local_err = NULL;
s = g_malloc0(sizeof(SerialState));
s->irq = irq;
s->baudbase = baudbase;
qemu_chr_fe_init(&s->chr, chr, &error_abort);
serial_realize_core(s, &error_fatal);
vmstate_register(NULL, base, &vmstate_serial, s);
object_property_set_bool(OBJECT(s), true, "realized", &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
memory_region_init_io(&s->io, NULL, &serial_io_ops, s, "serial", 8);
memory_region_add_subregion(system_io, base, &s->io);
return s;
sysbus_init_mmio(SYS_BUS_DEVICE(sio), &s->io);
sysbus_init_irq(SYS_BUS_DEVICE(sio), &s->irq);
}
static void serial_io_class_init(ObjectClass *klass, void* data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = serial_io_realize;
/* No dc->vmsd: class has no migratable state */
}
static void serial_io_instance_init(Object *o)
{
SerialIO *sio = SERIAL_IO(o);
object_initialize_child(o, "serial", &sio->serial, sizeof(sio->serial),
TYPE_SERIAL, &error_abort, NULL);
qdev_alias_all_properties(DEVICE(&sio->serial), o);
}
static const TypeInfo serial_io_info = {
.name = TYPE_SERIAL_IO,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SerialIO),
.instance_init = serial_io_instance_init,
.class_init = serial_io_class_init,
};
static Property serial_properties[] = {
DEFINE_PROP_CHR("chardev", SerialState, chr),
DEFINE_PROP_UINT32("baudbase", SerialState, baudbase, 115200),
DEFINE_PROP_END_OF_LIST(),
};
static void serial_class_init(ObjectClass *klass, void* data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
/* internal device for serialio/serialmm, not user-creatable */
dc->user_creatable = false;
dc->realize = serial_realize;
dc->unrealize = serial_unrealize;
dc->vmsd = &vmstate_serial;
dc->props = serial_properties;
}
static const TypeInfo serial_info = {
.name = TYPE_SERIAL,
.parent = TYPE_DEVICE,
.instance_size = sizeof(SerialState),
.class_init = serial_class_init,
};
/* Memory mapped interface */
static uint64_t serial_mm_read(void *opaque, hwaddr addr,
unsigned size)
{
SerialState *s = opaque;
return serial_ioport_read(s, addr >> s->it_shift, 1);
SerialMM *s = SERIAL_MM(opaque);
return serial_ioport_read(&s->serial, addr >> s->regshift, 1);
}
static void serial_mm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
SerialState *s = opaque;
SerialMM *s = SERIAL_MM(opaque);
value &= 255;
serial_ioport_write(s, addr >> s->it_shift, value, 1);
serial_ioport_write(&s->serial, addr >> s->regshift, value, 1);
}
static const MemoryRegionOps serial_mm_ops[3] = {
@ -1040,25 +1094,89 @@ static const MemoryRegionOps serial_mm_ops[3] = {
},
};
SerialState *serial_mm_init(MemoryRegion *address_space,
hwaddr base, int it_shift,
qemu_irq irq, int baudbase,
Chardev *chr, enum device_endian end)
static void serial_mm_realize(DeviceState *dev, Error **errp)
{
SerialState *s;
SerialMM *smm = SERIAL_MM(dev);
SerialState *s = &smm->serial;
Error *local_err = NULL;
s = g_malloc0(sizeof(SerialState));
object_property_set_bool(OBJECT(s), true, "realized", &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
s->it_shift = it_shift;
s->irq = irq;
s->baudbase = baudbase;
qemu_chr_fe_init(&s->chr, chr, &error_abort);
serial_realize_core(s, &error_fatal);
vmstate_register(NULL, base, &vmstate_serial, s);
memory_region_init_io(&s->io, NULL, &serial_mm_ops[end], s,
"serial", 8 << it_shift);
memory_region_add_subregion(address_space, base, &s->io);
return s;
memory_region_init_io(&s->io, NULL, &serial_mm_ops[smm->endianness], smm,
"serial", 8 << smm->regshift);
sysbus_init_mmio(SYS_BUS_DEVICE(smm), &s->io);
sysbus_init_irq(SYS_BUS_DEVICE(smm), &smm->serial.irq);
}
SerialMM *serial_mm_init(MemoryRegion *address_space,
hwaddr base, int regshift,
qemu_irq irq, int baudbase,
Chardev *chr, enum device_endian end)
{
SerialMM *smm = SERIAL_MM(qdev_create(NULL, TYPE_SERIAL_MM));
MemoryRegion *mr;
qdev_prop_set_uint8(DEVICE(smm), "regshift", regshift);
qdev_prop_set_uint32(DEVICE(smm), "baudbase", baudbase);
qdev_prop_set_chr(DEVICE(smm), "chardev", chr);
qdev_set_legacy_instance_id(DEVICE(smm), base, 2);
qdev_prop_set_uint8(DEVICE(smm), "endianness", end);
qdev_init_nofail(DEVICE(smm));
sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, irq);
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(smm), 0);
memory_region_add_subregion(address_space, base, mr);
return smm;
}
static void serial_mm_instance_init(Object *o)
{
SerialMM *smm = SERIAL_MM(o);
object_initialize_child(o, "serial", &smm->serial, sizeof(smm->serial),
TYPE_SERIAL, &error_abort, NULL);
qdev_alias_all_properties(DEVICE(&smm->serial), o);
}
static Property serial_mm_properties[] = {
/*
* Set the spacing between adjacent memory-mapped UART registers.
* Each register will be at (1 << regshift) bytes after the
* previous one.
*/
DEFINE_PROP_UINT8("regshift", SerialMM, regshift, 0),
DEFINE_PROP_UINT8("endianness", SerialMM, endianness, DEVICE_NATIVE_ENDIAN),
DEFINE_PROP_END_OF_LIST(),
};
static void serial_mm_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
dc->props = serial_mm_properties;
dc->realize = serial_mm_realize;
}
static const TypeInfo serial_mm_info = {
.name = TYPE_SERIAL_MM,
.parent = TYPE_SYS_BUS_DEVICE,
.class_init = serial_mm_class_init,
.instance_init = serial_mm_instance_init,
.instance_size = sizeof(SerialMM),
.class_init = serial_mm_class_init,
};
static void serial_register_types(void)
{
type_register_static(&serial_info);
type_register_static(&serial_io_info);
type_register_static(&serial_mm_info);
}
type_init(serial_register_types)

18
hw/core/qdev-properties.c
View File

@ -501,13 +501,6 @@ const PropertyInfo qdev_prop_string = {
.set = set_string,
};
/* --- pointer --- */
/* Not a proper property, just for dirty hacks. TODO Remove it! */
const PropertyInfo qdev_prop_ptr = {
.name = "ptr",
};
/* --- mac address --- */
/*
@ -1165,17 +1158,6 @@ void qdev_prop_set_enum(DeviceState *dev, const char *name, int value)
name, &error_abort);
}
void qdev_prop_set_ptr(DeviceState *dev, const char *name, void *value)
{
Property *prop;
void **ptr;
prop = qdev_prop_find(dev, name);
assert(prop && prop->info == &qdev_prop_ptr);
ptr = qdev_get_prop_ptr(dev, prop);
*ptr = value;
}
static GPtrArray *global_props(void)
{
static GPtrArray *gp;

15
hw/core/qdev.c
View File

@ -394,11 +394,8 @@ static NamedGPIOList *qdev_get_named_gpio_list(DeviceState *dev,
NamedGPIOList *ngl;
QLIST_FOREACH(ngl, &dev->gpios, node) {
/* NULL is a valid and matchable name, otherwise do a normal
* strcmp match.
*/
if ((!ngl->name && !name) ||
(name && ngl->name && strcmp(name, ngl->name) == 0)) {
/* NULL is a valid and matchable name. */
if (g_strcmp0(name, ngl->name) == 0) {
return ngl;
}
}
@ -739,14 +736,6 @@ void qdev_property_add_static(DeviceState *dev, Property *prop,
if (prop->info->create) {
prop->info->create(obj, prop, &local_err);
} else {
/*
* TODO qdev_prop_ptr does not have getters or setters. It must
* go now that it can be replaced with links. The test should be
* removed along with it: all static properties are read/write.
*/
if (!prop->info->get && !prop->info->set) {
return;
}
object_property_add(obj, prop->name, prop->info->name,
prop->info->get, prop->info->set,
prop->info->release,

32
hw/core/sysbus.c
View File

@ -250,38 +250,6 @@ DeviceState *sysbus_create_varargs(const char *name,
return dev;
}
DeviceState *sysbus_try_create_varargs(const char *name,
hwaddr addr, ...)
{
DeviceState *dev;
SysBusDevice *s;
va_list va;
qemu_irq irq;
int n;
dev = qdev_try_create(NULL, name);
if (!dev) {
return NULL;
}
s = SYS_BUS_DEVICE(dev);
qdev_init_nofail(dev);
if (addr != (hwaddr)-1) {
sysbus_mmio_map(s, 0, addr);
}
va_start(va, addr);
n = 0;
while (1) {
irq = va_arg(va, qemu_irq);
if (!irq) {
break;
}
sysbus_connect_irq(s, n, irq);
n++;
}
va_end(va);
return dev;
}
static void sysbus_dev_print(Monitor *mon, DeviceState *dev, int indent)
{
SysBusDevice *s = SYS_BUS_DEVICE(dev);

4
hw/cris/axis_dev88.c
View File

@ -253,7 +253,6 @@ void axisdev88_init(MachineState *machine)
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
CRISCPU *cpu;
CPUCRISState *env;
DeviceState *dev;
SysBusDevice *s;
DriveInfo *nand;
@ -267,7 +266,6 @@ void axisdev88_init(MachineState *machine)
/* init CPUs */
cpu = CRIS_CPU(cpu_create(machine->cpu_type));
env = &cpu->env;
/* allocate RAM */
memory_region_allocate_system_memory(phys_ram, NULL, "axisdev88.ram",
@ -297,8 +295,6 @@ void axisdev88_init(MachineState *machine)
dev = qdev_create(NULL, "etraxfs,pic");
/* FIXME: Is there a proper way to signal vectors to the CPU core? */
qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, 0x3001c000);

31
hw/display/sm501.c
View File

@ -1930,7 +1930,7 @@ typedef struct {
SM501State state;
uint32_t vram_size;
uint32_t base;
void *chr_state;
SerialMM serial;
} SM501SysBusState;
static void sm501_realize_sysbus(DeviceState *dev, Error **errp)
@ -1938,6 +1938,7 @@ static void sm501_realize_sysbus(DeviceState *dev, Error **errp)
SM501SysBusState *s = SYSBUS_SM501(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
DeviceState *usb_dev;
MemoryRegion *mr;
sm501_init(&s->state, dev, s->vram_size);
if (get_local_mem_size(&s->state) != s->vram_size) {
@ -1958,17 +1959,15 @@ static void sm501_realize_sysbus(DeviceState *dev, Error **errp)
sysbus_pass_irq(sbd, SYS_BUS_DEVICE(usb_dev));
/* bridge to serial emulation module */
if (s->chr_state) {
serial_mm_init(&s->state.mmio_region, SM501_UART0, 2,
NULL, /* TODO : chain irq to IRL */
115200, s->chr_state, DEVICE_LITTLE_ENDIAN);
}
qdev_init_nofail(DEVICE(&s->serial));
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->serial), 0);
memory_region_add_subregion(&s->state.mmio_region, SM501_UART0, mr);
/* TODO : chain irq to IRL */
}
static Property sm501_sysbus_properties[] = {
DEFINE_PROP_UINT32("vram-size", SM501SysBusState, vram_size, 0),
DEFINE_PROP_UINT32("base", SM501SysBusState, base, 0),
DEFINE_PROP_PTR("chr-state", SM501SysBusState, chr_state),
DEFINE_PROP_END_OF_LIST(),
};
@ -1999,9 +1998,20 @@ static void sm501_sysbus_class_init(ObjectClass *klass, void *data)
dc->props = sm501_sysbus_properties;
dc->reset = sm501_reset_sysbus;
dc->vmsd = &vmstate_sm501_sysbus;
/* Note: pointer property "chr-state" may remain null, thus
* no need for dc->user_creatable = false;
*/
}
static void sm501_sysbus_init(Object *o)
{
SM501SysBusState *sm501 = SYSBUS_SM501(o);
SerialMM *smm = &sm501->serial;
sysbus_init_child_obj(o, "serial", smm, sizeof(SerialMM), TYPE_SERIAL_MM);
qdev_set_legacy_instance_id(DEVICE(smm), SM501_UART0, 2);
qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
object_property_add_alias(o, "chardev",
OBJECT(smm), "chardev", &error_abort);
}
static const TypeInfo sm501_sysbus_info = {
@ -2009,6 +2019,7 @@ static const TypeInfo sm501_sysbus_info = {
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SM501SysBusState),
.class_init = sm501_sysbus_class_init,
.instance_init = sm501_sysbus_init,
};
#define TYPE_PCI_SM501 "sm501"

2
hw/dma/sparc32_dma.c
View File

@ -346,7 +346,7 @@ static void sparc32_ledma_device_realize(DeviceState *dev, Error **errp)
d = qdev_create(NULL, TYPE_LANCE);
object_property_add_child(OBJECT(dev), "lance", OBJECT(d), errp);
qdev_set_nic_properties(d, nd);
qdev_prop_set_ptr(d, "dma", dev);
object_property_set_link(OBJECT(d), OBJECT(dev), "dma", errp);
qdev_init_nofail(d);
}

42
hw/gpio/omap_gpio.c
View File

@ -40,10 +40,6 @@ struct omap_gpio_s {
uint16_t pins;
};
#define TYPE_OMAP1_GPIO "omap-gpio"
#define OMAP1_GPIO(obj) \
OBJECT_CHECK(struct omap_gpif_s, (obj), TYPE_OMAP1_GPIO)
struct omap_gpif_s {
SysBusDevice parent_obj;
@ -212,10 +208,6 @@ struct omap2_gpio_s {
uint8_t delay;
};
#define TYPE_OMAP2_GPIO "omap2-gpio"
#define OMAP2_GPIO(obj) \
OBJECT_CHECK(struct omap2_gpif_s, (obj), TYPE_OMAP2_GPIO)
struct omap2_gpif_s {
SysBusDevice parent_obj;
@ -747,21 +739,13 @@ static void omap2_gpio_realize(DeviceState *dev, Error **errp)
}
}
/* Using qdev pointer properties for the clocks is not ideal.
* qdev should support a generic means of defining a 'port' with
* an arbitrary interface for connecting two devices. Then we
* could reframe the omap clock API in terms of clock ports,
* and get some type safety. For now the best qdev provides is
* passing an arbitrary pointer.
* (It's not possible to pass in the string which is the clock
* name, because this device does not have the necessary information
* (ie the struct omap_mpu_state_s*) to do the clockname to pointer
* translation.)
*/
void omap_gpio_set_clk(omap_gpif *gpio, omap_clk clk)
{
gpio->clk = clk;
}
static Property omap_gpio_properties[] = {
DEFINE_PROP_INT32("mpu_model", struct omap_gpif_s, mpu_model, 0),
DEFINE_PROP_PTR("clk", struct omap_gpif_s, clk),
DEFINE_PROP_END_OF_LIST(),
};
@ -784,15 +768,19 @@ static const TypeInfo omap_gpio_info = {
.class_init = omap_gpio_class_init,
};
void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk)
{
gpio->iclk = clk;
}
void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk)
{
assert(i <= 5);
gpio->fclk[i] = clk;
}
static Property omap2_gpio_properties[] = {
DEFINE_PROP_INT32("mpu_model", struct omap2_gpif_s, mpu_model, 0),
DEFINE_PROP_PTR("iclk", struct omap2_gpif_s, iclk),
DEFINE_PROP_PTR("fclk0", struct omap2_gpif_s, fclk[0]),
DEFINE_PROP_PTR("fclk1", struct omap2_gpif_s, fclk[1]),
DEFINE_PROP_PTR("fclk2", struct omap2_gpif_s, fclk[2]),
DEFINE_PROP_PTR("fclk3", struct omap2_gpif_s, fclk[3]),
DEFINE_PROP_PTR("fclk4", struct omap2_gpif_s, fclk[4]),
DEFINE_PROP_PTR("fclk5", struct omap2_gpif_s, fclk[5]),
DEFINE_PROP_END_OF_LIST(),
};

19
hw/i2c/omap_i2c.c
View File

@ -28,10 +28,7 @@
#include "qemu/error-report.h"
#include "qapi/error.h"
#define TYPE_OMAP_I2C "omap_i2c"
#define OMAP_I2C(obj) OBJECT_CHECK(OMAPI2CState, (obj), TYPE_OMAP_I2C)
typedef struct OMAPI2CState {
struct OMAPI2CState {
SysBusDevice parent_obj;
MemoryRegion iomem;
@ -56,7 +53,7 @@ typedef struct OMAPI2CState {
uint8_t divider;
uint8_t times[2];
uint16_t test;
} OMAPI2CState;
};
#define OMAP2_INTR_REV 0x34
#define OMAP2_GC_REV 0x34
@ -504,10 +501,18 @@ static void omap_i2c_realize(DeviceState *dev, Error **errp)
}
}
void omap_i2c_set_iclk(OMAPI2CState *i2c, omap_clk clk)
{
i2c->iclk = clk;
}
void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk)
{
i2c->fclk = clk;
}
static Property omap_i2c_properties[] = {
DEFINE_PROP_UINT8("revision", OMAPI2CState, revision, 0),
DEFINE_PROP_PTR("iclk", OMAPI2CState, iclk),
DEFINE_PROP_PTR("fclk", OMAPI2CState, fclk),
DEFINE_PROP_END_OF_LIST(),
};

20
hw/i2c/smbus_eeprom.c
View File

@ -44,7 +44,7 @@
typedef struct SMBusEEPROMDevice {
SMBusDevice smbusdev;
uint8_t data[SMBUS_EEPROM_SIZE];
void *init_data;
uint8_t *init_data;
uint8_t offset;
bool accessed;
} SMBusEEPROMDevice;
@ -129,13 +129,13 @@ static void smbus_eeprom_reset(DeviceState *dev)
static void smbus_eeprom_realize(DeviceState *dev, Error **errp)
{
smbus_eeprom_reset(dev);
}
SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev);
static Property smbus_eeprom_properties[] = {
DEFINE_PROP_PTR("data", SMBusEEPROMDevice, init_data),
DEFINE_PROP_END_OF_LIST(),
};
smbus_eeprom_reset(dev);
if (eeprom->init_data == NULL) {
error_setg(errp, "init_data cannot be NULL");
}
}
static void smbus_eeprom_class_initfn(ObjectClass *klass, void *data)
{
@ -146,9 +146,8 @@ static void smbus_eeprom_class_initfn(ObjectClass *klass, void *data)
dc->reset = smbus_eeprom_reset;
sc->receive_byte = eeprom_receive_byte;
sc->write_data = eeprom_write_data;
dc->props = smbus_eeprom_properties;
dc->vmsd = &vmstate_smbus_eeprom;
/* Reason: pointer property "data" */
/* Reason: init_data */
dc->user_creatable = false;
}
@ -172,7 +171,8 @@ void smbus_eeprom_init_one(I2CBus *smbus, uint8_t address, uint8_t *eeprom_buf)
dev = qdev_create((BusState *) smbus, TYPE_SMBUS_EEPROM);
qdev_prop_set_uint8(dev, "address", address);
qdev_prop_set_ptr(dev, "data", eeprom_buf);
/* FIXME: use an array of byte or block backend property? */
SMBUS_EEPROM(dev)->init_data = eeprom_buf;
qdev_init_nofail(dev);
}

7
hw/i386/pc.c
View File

@ -1156,9 +1156,9 @@ static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
vmmouse = NULL;
}
if (vmmouse) {
DeviceState *dev = DEVICE(vmmouse);
qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
qdev_init_nofail(dev);
object_property_set_link(OBJECT(vmmouse), OBJECT(i8042),
"i8042", &error_abort);
qdev_init_nofail(DEVICE(vmmouse));
}
port92 = isa_create_simple(isa_bus, TYPE_PORT92);
@ -1198,7 +1198,6 @@ void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
* when the HPET wants to take over. Thus we have to disable the latter.
*/
if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
/* In order to set property, here not using sysbus_try_create_simple */
hpet = qdev_try_create(NULL, TYPE_HPET);
if (hpet) {
/* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7

8
hw/i386/vmmouse.c
View File

@ -66,7 +66,7 @@ typedef struct VMMouseState
uint16_t status;
uint8_t absolute;
QEMUPutMouseEntry *entry;
void *ps2_mouse;
ISAKBDState *i8042;
} VMMouseState;
static uint32_t vmmouse_get_status(VMMouseState *s)
@ -105,7 +105,7 @@ static void vmmouse_mouse_event(void *opaque, int x, int y, int dz, int buttons_
/* need to still generate PS2 events to notify driver to
read from queue */
i8042_isa_mouse_fake_event(s->ps2_mouse);
i8042_isa_mouse_fake_event(s->i8042);
}
static void vmmouse_remove_handler(VMMouseState *s)
@ -275,7 +275,7 @@ static void vmmouse_realizefn(DeviceState *dev, Error **errp)
}
static Property vmmouse_properties[] = {
DEFINE_PROP_PTR("ps2_mouse", VMMouseState, ps2_mouse),
DEFINE_PROP_LINK("i8042", VMMouseState, i8042, TYPE_I8042, ISAKBDState *),
DEFINE_PROP_END_OF_LIST(),
};
@ -287,8 +287,6 @@ static void vmmouse_class_initfn(ObjectClass *klass, void *data)
dc->reset = vmmouse_reset;
dc->vmsd = &vmstate_vmmouse;
dc->props = vmmouse_properties;
/* Reason: pointer property "ps2_mouse" */
dc->user_creatable = false;
}
static const TypeInfo vmmouse_info = {

8
hw/input/pckbd.c
View File

@ -482,17 +482,15 @@ void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
#define I8042(obj) OBJECT_CHECK(ISAKBDState, (obj), TYPE_I8042)
typedef struct ISAKBDState {
struct ISAKBDState {
ISADevice parent_obj;
KBDState kbd;
MemoryRegion io[2];
} ISAKBDState;
};
void i8042_isa_mouse_fake_event(void *opaque)
void i8042_isa_mouse_fake_event(ISAKBDState *isa)
{
ISADevice *dev = opaque;
ISAKBDState *isa = I8042(dev);
KBDState *s = &isa->kbd;
ps2_mouse_fake_event(s->mouse);

26
hw/intc/etraxfs_pic.c
View File

@ -27,8 +27,6 @@
#include "qemu/module.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
//#include "pc.h"
//#include "etraxfs.h"
#define D(x)
@ -48,7 +46,6 @@ struct etrax_pic
SysBusDevice parent_obj;
MemoryRegion mmio;
void *interrupt_vector;
qemu_irq parent_irq;
qemu_irq parent_nmi;
uint32_t regs[R_MAX];
@ -79,11 +76,7 @@ static void pic_update(struct etrax_pic *fs)
}
}
if (fs->interrupt_vector) {
/* hack alert: ptr property */
*(uint32_t*)(fs->interrupt_vector) = vector;
}
qemu_set_irq(fs->parent_irq, !!vector);
qemu_set_irq(fs->parent_irq, vector);
}
static uint64_t
@ -163,28 +156,11 @@ static void etraxfs_pic_init(Object *obj)
sysbus_init_mmio(sbd, &s->mmio);
}
static Property etraxfs_pic_properties[] = {
DEFINE_PROP_PTR("interrupt_vector", struct etrax_pic, interrupt_vector),
DEFINE_PROP_END_OF_LIST(),
};
static void etraxfs_pic_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->props = etraxfs_pic_properties;
/*
* Note: pointer property "interrupt_vector" may remain null, thus
* no need for dc->user_creatable = false;
*/
}
static const TypeInfo etraxfs_pic_info = {
.name = TYPE_ETRAX_FS_PIC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(struct etrax_pic),
.instance_init = etraxfs_pic_init,
.class_init = etraxfs_pic_class_init,
};
static void etraxfs_pic_register_types(void)

35
hw/intc/grlib_irqmp.c
View File

@ -25,6 +25,7 @@
*/
#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/sysbus.h"
#include "cpu.h"
@ -58,10 +59,8 @@ typedef struct IRQMP {
MemoryRegion iomem;
void *set_pil_in;
void *set_pil_in_opaque;
IRQMPState *state;
qemu_irq irq;
} IRQMP;
struct IRQMPState {
@ -82,7 +81,6 @@ static void grlib_irqmp_check_irqs(IRQMPState *state)
uint32_t pend = 0;
uint32_t level0 = 0;
uint32_t level1 = 0;
set_pil_in_fn set_pil_in;
assert(state != NULL);
assert(state->parent != NULL);
@ -97,14 +95,8 @@ static void grlib_irqmp_check_irqs(IRQMPState *state)
trace_grlib_irqmp_check_irqs(state->pending, state->force[0],
state->mask[0], level1, level0);
set_pil_in = (set_pil_in_fn)state->parent->set_pil_in;
/* Trigger level1 interrupt first and level0 if there is no level1 */
if (level1 != 0) {
set_pil_in(state->parent->set_pil_in_opaque, level1);
} else {
set_pil_in(state->parent->set_pil_in_opaque, level0);
}
qemu_set_irq(state->parent->irq, level1 ?: level0);
}
static void grlib_irqmp_ack_mask(IRQMPState *state, uint32_t mask)
@ -335,6 +327,7 @@ static void grlib_irqmp_init(Object *obj)
IRQMP *irqmp = GRLIB_IRQMP(obj);
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
qdev_init_gpio_out_named(DEVICE(obj), &irqmp->irq, "grlib-irq", 1);
memory_region_init_io(&irqmp->iomem, obj, &grlib_irqmp_ops, irqmp,
"irqmp", IRQMP_REG_SIZE);
@ -343,31 +336,11 @@ static void grlib_irqmp_init(Object *obj)
sysbus_init_mmio(dev, &irqmp->iomem);
}
static void grlib_irqmp_realize(DeviceState *dev, Error **errp)
{
IRQMP *irqmp = GRLIB_IRQMP(dev);
/* Check parameters */
if (irqmp->set_pil_in == NULL) {
error_setg(errp, "set_pil_in cannot be NULL.");
}
}
static Property grlib_irqmp_properties[] = {
DEFINE_PROP_PTR("set_pil_in", IRQMP, set_pil_in),
DEFINE_PROP_PTR("set_pil_in_opaque", IRQMP, set_pil_in_opaque),
DEFINE_PROP_END_OF_LIST(),
};
static void grlib_irqmp_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = grlib_irqmp_reset;
dc->props = grlib_irqmp_properties;
/* Reason: pointer properties "set_pil_in", "set_pil_in_opaque" */
dc->user_creatable = false;
dc->realize = grlib_irqmp_realize;
}
static const TypeInfo grlib_irqmp_info = {

17
hw/intc/omap_intc.c
View File

@ -38,10 +38,6 @@ struct omap_intr_handler_bank_s {
unsigned char priority[32];
};
#define TYPE_OMAP_INTC "common-omap-intc"
#define OMAP_INTC(obj) \
OBJECT_CHECK(struct omap_intr_handler_s, (obj), TYPE_OMAP_INTC)
struct omap_intr_handler_s {
SysBusDevice parent_obj;
@ -391,9 +387,18 @@ static void omap_intc_realize(DeviceState *dev, Error **errp)
}
}
void omap_intc_set_iclk(omap_intr_handler *intc, omap_clk clk)
{
intc->iclk = clk;
}
void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk)
{
intc->fclk = clk;
}
static Property omap_intc_properties[] = {
DEFINE_PROP_UINT32("size", struct omap_intr_handler_s, size, 0x100),
DEFINE_PROP_PTR("clk", struct omap_intr_handler_s, iclk),
DEFINE_PROP_END_OF_LIST(),
};
@ -647,8 +652,6 @@ static void omap2_intc_realize(DeviceState *dev, Error **errp)
static Property omap2_intc_properties[] = {
DEFINE_PROP_UINT8("revision", struct omap_intr_handler_s,
revision, 0x21),
DEFINE_PROP_PTR("iclk", struct omap_intr_handler_s, iclk),
DEFINE_PROP_PTR("fclk", struct omap_intr_handler_s, fclk),
DEFINE_PROP_END_OF_LIST(),
};

3
hw/m68k/q800.c
View File

@ -266,7 +266,8 @@ static void q800_init(MachineState *machine)
qdev_set_nic_properties(dev, &nd_table[0]);
qdev_prop_set_uint8(dev, "it_shift", 2);
qdev_prop_set_bit(dev, "big_endian", true);
qdev_prop_set_ptr(dev, "dma_mr", get_system_memory());
object_property_set_link(OBJECT(dev), OBJECT(get_system_memory()),
"dma_mr", &error_abort);
qdev_init_nofail(dev);
sysbus = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(sysbus, 0, SONIC_BASE);

2
hw/mips/boston.c
View File

@ -50,7 +50,7 @@ typedef struct {
MachineState *mach;
MIPSCPSState cps;
SerialState *uart;
SerialMM *uart;
CharBackend lcd_display;
char lcd_content[8];

2
hw/mips/cps.c
View File

@ -106,7 +106,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
object_property_set_bool(OBJECT(&s->itu), saar_present, "saar-present",
&err);
if (saar_present) {
qdev_prop_set_ptr(DEVICE(&s->itu), "saar", (void *)&env->CP0_SAAR);
s->itu.saar = &env->CP0_SAAR;
}
object_property_set_bool(OBJECT(&s->itu), true, "realized", &err);
if (err != NULL) {

3
hw/mips/mips_jazz.c
View File

@ -290,7 +290,8 @@ static void mips_jazz_init(MachineState *machine,
dev = qdev_create(NULL, "dp8393x");
qdev_set_nic_properties(dev, nd);
qdev_prop_set_uint8(dev, "it_shift", 2);
qdev_prop_set_ptr(dev, "dma_mr", rc4030_dma_mr);
object_property_set_link(OBJECT(dev), OBJECT(rc4030_dma_mr),
"dma_mr", &error_abort);
qdev_init_nofail(dev);
sysbus = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(sysbus, 0, 0x80001000);

2
hw/mips/mips_malta.c
View File

@ -83,7 +83,7 @@ typedef struct {
uint32_t i2csel;
CharBackend display;
char display_text[9];
SerialState *uart;
SerialMM *uart;
bool display_inited;
} MaltaFPGAState;

14
hw/mips/mips_mipssim.c
View File

@ -40,6 +40,7 @@
#include "hw/loader.h"
#include "elf.h"
#include "hw/sysbus.h"
#include "hw/qdev-properties.h"
#include "exec/address-spaces.h"
#include "qemu/error-report.h"
#include "sysemu/qtest.h"
@ -219,9 +220,16 @@ mips_mipssim_init(MachineState *machine)
* A single 16450 sits at offset 0x3f8. It is attached to
* MIPS CPU INT2, which is interrupt 4.
*/
if (serial_hd(0))
serial_init(0x3f8, env->irq[4], 115200, serial_hd(0),
get_system_io());
if (serial_hd(0)) {
DeviceState *dev = qdev_create(NULL, TYPE_SERIAL_IO);
qdev_prop_set_chr(dev, "chardev", serial_hd(0));
qdev_set_legacy_instance_id(dev, 0x3f8, 2);
qdev_init_nofail(dev);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, env->irq[4]);
sysbus_add_io(SYS_BUS_DEVICE(dev), 0x3f8,
sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0));
}
if (nd_table[0].used)
/* MIPSnet uses the MIPS CPU INT0, which is interrupt 2. */

7
hw/net/dp8393x.c
View File

@ -175,7 +175,7 @@ typedef struct dp8393xState {
int loopback_packet;
/* Memory access */
void *dma_mr;
MemoryRegion *dma_mr;
AddressSpace as;
} dp8393xState;
@ -948,7 +948,8 @@ static const VMStateDescription vmstate_dp8393x = {
static Property dp8393x_properties[] = {
DEFINE_NIC_PROPERTIES(dp8393xState, conf),
DEFINE_PROP_PTR("dma_mr", dp8393xState, dma_mr),
DEFINE_PROP_LINK("dma_mr", dp8393xState, dma_mr,
TYPE_MEMORY_REGION, MemoryRegion *),
DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0),
DEFINE_PROP_BOOL("big_endian", dp8393xState, big_endian, false),
DEFINE_PROP_END_OF_LIST(),
@ -963,8 +964,6 @@ static void dp8393x_class_init(ObjectClass *klass, void *data)
dc->reset = dp8393x_reset;
dc->vmsd = &vmstate_dp8393x;
dc->props = dp8393x_properties;
/* Reason: dma_mr property can't be set */
dc->user_creatable = false;
}
static const TypeInfo dp8393x_info = {

44
hw/net/etraxfs_eth.c
View File

@ -338,14 +338,8 @@ typedef struct ETRAXFSEthState
uint8_t macaddr[2][6];
uint32_t regs[FS_ETH_MAX_REGS];
union {
void *vdma_out;
struct etraxfs_dma_client *dma_out;
};
union {
void *vdma_in;
struct etraxfs_dma_client *dma_in;
};
struct etraxfs_dma_client *dma_out;
struct etraxfs_dma_client *dma_in;
/* MDIO bus. */
struct qemu_mdio mdio_bus;
@ -635,8 +629,6 @@ static void etraxfs_eth_realize(DeviceState *dev, Error **errp)
static Property etraxfs_eth_properties[] = {
DEFINE_PROP_UINT32("phyaddr", ETRAXFSEthState, phyaddr, 1),
DEFINE_PROP_PTR("dma_out", ETRAXFSEthState, vdma_out),
DEFINE_PROP_PTR("dma_in", ETRAXFSEthState, vdma_in),
DEFINE_NIC_PROPERTIES(ETRAXFSEthState, conf),
DEFINE_PROP_END_OF_LIST(),
};
@ -648,10 +640,40 @@ static void etraxfs_eth_class_init(ObjectClass *klass, void *data)
dc->realize = etraxfs_eth_realize;
dc->reset = etraxfs_eth_reset;
dc->props = etraxfs_eth_properties;
/* Reason: pointer properties "dma_out", "dma_in" */
/* Reason: dma_out, dma_in are not user settable */
dc->user_creatable = false;
}
/* Instantiate an ETRAXFS Ethernet MAC. */
DeviceState *
etraxfs_eth_init(NICInfo *nd, hwaddr base, int phyaddr,
struct etraxfs_dma_client *dma_out,
struct etraxfs_dma_client *dma_in)
{
DeviceState *dev;
qemu_check_nic_model(nd, "fseth");
dev = qdev_create(NULL, "etraxfs-eth");
qdev_set_nic_properties(dev, nd);
qdev_prop_set_uint32(dev, "phyaddr", phyaddr);
/*
* TODO: QOM design, define a QOM interface for "I am an etraxfs
* DMA client" (which replaces the current 'struct
* etraxfs_dma_client' ad-hoc interface), implement it on the
* ethernet device, and then have QOM link properties on the DMA
* controller device so that you can pass the interface
* implementations to it.
*/
ETRAX_FS_ETH(dev)->dma_out = dma_out;
ETRAX_FS_ETH(dev)->dma_in = dma_in;
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
return dev;
}
static const TypeInfo etraxfs_eth_info = {
.name = TYPE_ETRAX_FS_ETH,
.parent = TYPE_SYS_BUS_DEVICE,

5
hw/net/lance.c
View File

@ -138,7 +138,8 @@ static void lance_instance_init(Object *obj)
}
static Property lance_properties[] = {
DEFINE_PROP_PTR("dma", SysBusPCNetState, state.dma_opaque),
DEFINE_PROP_LINK("dma", SysBusPCNetState, state.dma_opaque,
TYPE_DEVICE, DeviceState *),
DEFINE_NIC_PROPERTIES(SysBusPCNetState, state.conf),
DEFINE_PROP_END_OF_LIST(),
};
@ -153,8 +154,6 @@ static void lance_class_init(ObjectClass *klass, void *data)
dc->reset = lance_reset;
dc->vmsd = &vmstate_lance;
dc->props = lance_properties;
/* Reason: pointer property "dma" */
dc->user_creatable = false;
}
static const TypeInfo lance_info = {

2
hw/net/pcnet-pci.c
View File

@ -231,7 +231,7 @@ static void pci_pcnet_realize(PCIDevice *pci_dev, Error **errp)
s->irq = pci_allocate_irq(pci_dev);
s->phys_mem_read = pci_physical_memory_read;
s->phys_mem_write = pci_physical_memory_write;
s->dma_opaque = pci_dev;
s->dma_opaque = DEVICE(pci_dev);
pcnet_common_init(DEVICE(pci_dev), s, &net_pci_pcnet_info);
}

2
hw/net/pcnet.h
View File

@ -50,7 +50,7 @@ struct PCNetState_st {
uint8_t *buf, int len, int do_bswap);
void (*phys_mem_write)(void *dma_opaque, hwaddr addr,
uint8_t *buf, int len, int do_bswap);
void *dma_opaque;
DeviceState *dma_opaque;
int tx_busy;
int looptest;
};

2
hw/sh4/r2d.c
View File

@ -272,7 +272,7 @@ static void r2d_init(MachineState *machine)
busdev = SYS_BUS_DEVICE(dev);
qdev_prop_set_uint32(dev, "vram-size", SM501_VRAM_SIZE);
qdev_prop_set_uint32(dev, "base", 0x10000000);
qdev_prop_set_ptr(dev, "chr-state", serial_hd(2));
qdev_prop_set_chr(dev, "chardev", serial_hd(2));
qdev_init_nofail(dev);
sysbus_mmio_map(busdev, 0, 0x10000000);
sysbus_mmio_map(busdev, 1, 0x13e00000);

15
hw/sparc/leon3.c
View File

@ -143,9 +143,14 @@ void leon3_irq_ack(void *irq_manager, int intno)
grlib_irqmp_ack((DeviceState *)irq_manager, intno);
}
static void leon3_set_pil_in(void *opaque, uint32_t pil_in)
/*
* This device assumes that the incoming 'level' value on the
* qemu_irq is the interrupt number, not just a simple 0/1 level.
*/
static void leon3_set_pil_in(void *opaque, int n, int level)
{
CPUSPARCState *env = (CPUSPARCState *)opaque;
CPUSPARCState *env = opaque;
uint32_t pil_in = level;
CPUState *cs;
assert(env != NULL);
@ -225,8 +230,10 @@ static void leon3_generic_hw_init(MachineState *machine)
/* Allocate IRQ manager */
dev = qdev_create(NULL, TYPE_GRLIB_IRQMP);
qdev_prop_set_ptr(dev, "set_pil_in", leon3_set_pil_in);
qdev_prop_set_ptr(dev, "set_pil_in_opaque", env);
qdev_init_gpio_in_named_with_opaque(DEVICE(cpu), leon3_set_pil_in,
env, "pil", 1);
qdev_connect_gpio_out_named(dev, "grlib-irq", 0,
qdev_get_gpio_in_named(DEVICE(cpu), "pil", 0));
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_IRQMP_OFFSET);
env->irq_manager = dev;

52
include/hw/arm/omap.h
View File

@ -67,6 +67,58 @@ void omap_clk_setrate(omap_clk clk, int divide, int multiply);
int64_t omap_clk_getrate(omap_clk clk);
void omap_clk_reparent(omap_clk clk, omap_clk parent);
/* omap_intc.c */
#define TYPE_OMAP_INTC "common-omap-intc"
#define OMAP_INTC(obj) \
OBJECT_CHECK(omap_intr_handler, (obj), TYPE_OMAP_INTC)
typedef struct omap_intr_handler_s omap_intr_handler;
/*
* TODO: Ideally we should have a clock framework that
* let us wire these clocks up with QOM properties or links.
*
* qdev should support a generic means of defining a 'port' with
* an arbitrary interface for connecting two devices. Then we
* could reframe the omap clock API in terms of clock ports,
* and get some type safety. For now the best qdev provides is
* passing an arbitrary pointer.
* (It's not possible to pass in the string which is the clock
* name, because this device does not have the necessary information
* (ie the struct omap_mpu_state_s*) to do the clockname to pointer
* translation.)
*/
void omap_intc_set_iclk(omap_intr_handler *intc, omap_clk clk);
void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk);
/* omap_i2c.c */
#define TYPE_OMAP_I2C "omap_i2c"
#define OMAP_I2C(obj) OBJECT_CHECK(OMAPI2CState, (obj), TYPE_OMAP_I2C)
typedef struct OMAPI2CState OMAPI2CState;
/* TODO: clock framework (see above) */
void omap_i2c_set_iclk(OMAPI2CState *i2c, omap_clk clk);
void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk);
/* omap_gpio.c */
#define TYPE_OMAP1_GPIO "omap-gpio"
#define OMAP1_GPIO(obj) \
OBJECT_CHECK(struct omap_gpif_s, (obj), TYPE_OMAP1_GPIO)
#define TYPE_OMAP2_GPIO "omap2-gpio"
#define OMAP2_GPIO(obj) \
OBJECT_CHECK(struct omap2_gpif_s, (obj), TYPE_OMAP2_GPIO)
typedef struct omap_gpif_s omap_gpif;
typedef struct omap2_gpif_s omap2_gpif;
/* TODO: clock framework (see above) */
void omap_gpio_set_clk(omap_gpif *gpio, omap_clk clk);
void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk);
void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk);
/* OMAP2 l4 Interconnect */
struct omap_l4_s;
struct omap_l4_region_s {

43
include/hw/char/serial.h
View File

@ -30,10 +30,13 @@
#include "exec/memory.h"
#include "qemu/fifo8.h"
#include "chardev/char.h"
#include "hw/sysbus.h"
#define UART_FIFO_LENGTH 16 /* 16550A Fifo Length */
typedef struct SerialState {
DeviceState parent;
uint16_t divider;
uint8_t rbr; /* receive register */
uint8_t thr; /* transmit holding register */
@ -54,8 +57,7 @@ typedef struct SerialState {
qemu_irq irq;
CharBackend chr;
int last_break_enable;
int it_shift;
int baudbase;
uint32_t baudbase;
uint32_t tsr_retry;
guint watch_tag;
uint32_t wakeup;
@ -77,20 +79,39 @@ typedef struct SerialState {
MemoryRegion io;
} SerialState;
typedef struct SerialMM {
SysBusDevice parent;
SerialState serial;
uint8_t regshift;
uint8_t endianness;
} SerialMM;
typedef struct SerialIO {
SysBusDevice parent;
SerialState serial;
} SerialIO;
extern const VMStateDescription vmstate_serial;
extern const MemoryRegionOps serial_io_ops;
void serial_realize_core(SerialState *s, Error **errp);
void serial_exit_core(SerialState *s);
void serial_set_frequency(SerialState *s, uint32_t frequency);
/* legacy pre qom */
SerialState *serial_init(int base, qemu_irq irq, int baudbase,
Chardev *chr, MemoryRegion *system_io);
SerialState *serial_mm_init(MemoryRegion *address_space,
hwaddr base, int it_shift,
qemu_irq irq, int baudbase,
Chardev *chr, enum device_endian end);
#define TYPE_SERIAL "serial"
#define SERIAL(s) OBJECT_CHECK(SerialState, (s), TYPE_SERIAL)
#define TYPE_SERIAL_MM "serial-mm"
#define SERIAL_MM(s) OBJECT_CHECK(SerialMM, (s), TYPE_SERIAL_MM)
#define TYPE_SERIAL_IO "serial-io"
#define SERIAL_IO(s) OBJECT_CHECK(SerialIO, (s), TYPE_SERIAL_IO)
SerialMM *serial_mm_init(MemoryRegion *address_space,
hwaddr base, int regshift,
qemu_irq irq, int baudbase,
Chardev *chr, enum device_endian end);
/* serial-isa.c */

20
include/hw/cris/etraxfs.h
View File

@ -30,23 +30,9 @@
#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
/* Instantiate an ETRAXFS Ethernet MAC. */
static inline DeviceState *
etraxfs_eth_init(NICInfo *nd, hwaddr base, int phyaddr,
void *dma_out, void *dma_in)
{
DeviceState *dev;
qemu_check_nic_model(nd, "fseth");
dev = qdev_create(NULL, "etraxfs-eth");
qdev_set_nic_properties(dev, nd);
qdev_prop_set_uint32(dev, "phyaddr", phyaddr);
qdev_prop_set_ptr(dev, "dma_out", dma_out);
qdev_prop_set_ptr(dev, "dma_in", dma_in);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
return dev;
}
DeviceState *etraxfs_eth_init(NICInfo *nd, hwaddr base, int phyaddr,
struct etraxfs_dma_client *dma_out,
struct etraxfs_dma_client *dma_in);
static inline DeviceState *etraxfs_ser_create(hwaddr addr,
qemu_irq irq,

4
include/hw/input/i8042.h
View File

@ -14,10 +14,12 @@
#define I8042_A20_LINE "a20"
typedef struct ISAKBDState ISAKBDState;
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
MemoryRegion *region, ram_addr_t size,
hwaddr mask);
void i8042_isa_mouse_fake_event(void *opaque);
void i8042_isa_mouse_fake_event(ISAKBDState *isa);
void i8042_setup_a20_line(ISADevice *dev, qemu_irq a20_out);
#endif /* HW_INPUT_I8042_H */

24
include/hw/qdev-properties.h
View File

@ -18,7 +18,6 @@ extern const PropertyInfo qdev_prop_size;
extern const PropertyInfo qdev_prop_string;
extern const PropertyInfo qdev_prop_chr;
extern const PropertyInfo qdev_prop_tpm;
extern const PropertyInfo qdev_prop_ptr;
extern const PropertyInfo qdev_prop_macaddr;
extern const PropertyInfo qdev_prop_on_off_auto;
extern const PropertyInfo qdev_prop_losttickpolicy;
@ -171,25 +170,6 @@ extern const PropertyInfo qdev_prop_pcie_link_width;
#define DEFINE_PROP_PCI_DEVFN(_n, _s, _f, _d) \
DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_pci_devfn, int32_t)
/*
* Please avoid pointer properties. If you must use them, you must
* cover them in their device's class init function as follows:
*
* - If the property must be set, the device cannot be used with
* device_add, so add code like this:
* |* Reason: pointer property "NAME-OF-YOUR-PROP" *|
* DeviceClass *dc = DEVICE_CLASS(class);
* dc->user_creatable = false;
*
* - If the property may safely remain null, document it like this:
* |*
* * Note: pointer property "interrupt_vector" may remain null, thus
* * no need for dc->user_creatable = false;
* *|
*/
#define DEFINE_PROP_PTR(_n, _s, _f) \
DEFINE_PROP(_n, _s, _f, qdev_prop_ptr, void*)
#define DEFINE_PROP_CHR(_n, _s, _f) \
DEFINE_PROP(_n, _s, _f, qdev_prop_chr, CharBackend)
#define DEFINE_PROP_STRING(_n, _s, _f) \
@ -216,8 +196,6 @@ extern const PropertyInfo qdev_prop_pcie_link_width;
DEFINE_PROP_UNSIGNED(_n, _s, _f, 0, qdev_prop_blocksize, uint16_t)
#define DEFINE_PROP_PCI_HOST_DEVADDR(_n, _s, _f) \
DEFINE_PROP(_n, _s, _f, qdev_prop_pci_host_devaddr, PCIHostDeviceAddress)
#define DEFINE_PROP_MEMORY_REGION(_n, _s, _f) \
DEFINE_PROP(_n, _s, _f, qdev_prop_ptr, MemoryRegion *)
#define DEFINE_PROP_OFF_AUTO_PCIBAR(_n, _s, _f, _d) \
DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_off_auto_pcibar, \
OffAutoPCIBAR)
@ -264,8 +242,6 @@ void qdev_prop_set_drive(DeviceState *dev, const char *name,
void qdev_prop_set_macaddr(DeviceState *dev, const char *name,
const uint8_t *value);
void qdev_prop_set_enum(DeviceState *dev, const char *name, int value);
/* FIXME: Remove opaque pointer properties. */
void qdev_prop_set_ptr(DeviceState *dev, const char *name, void *value);
void qdev_prop_register_global(GlobalProperty *prop);
int qdev_prop_check_globals(void);

13
include/hw/sysbus.h
View File

@ -24,10 +24,6 @@ typedef struct SysBusDevice SysBusDevice;
/**
* SysBusDeviceClass:
* @init: Callback function invoked when the #DeviceState.realized property
* is changed to %true. Deprecated, new types inheriting directly from
* TYPE_SYS_BUS_DEVICE should use #DeviceClass.realize instead, new leaf
* types should consult their respective parent type.
*
* SysBusDeviceClass is not overriding #DeviceClass.realize, so derived
* classes overriding it are not required to invoke its implementation.
@ -117,8 +113,7 @@ void foreach_dynamic_sysbus_device(FindSysbusDeviceFunc *func, void *opaque);
/* Legacy helper function for creating devices. */
DeviceState *sysbus_create_varargs(const char *name,
hwaddr addr, ...);
DeviceState *sysbus_try_create_varargs(const char *name,
hwaddr addr, ...);
static inline DeviceState *sysbus_create_simple(const char *name,
hwaddr addr,
qemu_irq irq)
@ -126,11 +121,5 @@ static inline DeviceState *sysbus_create_simple(const char *name,
return sysbus_create_varargs(name, addr, irq, NULL);
}
static inline DeviceState *sysbus_try_create_simple(const char *name,
hwaddr addr,
qemu_irq irq)
{
return sysbus_try_create_varargs(name, addr, irq, NULL);
}
#endif /* HW_SYSBUS_H */

1
include/qemu/id.h
View File

@ -4,6 +4,7 @@
typedef enum IdSubSystems {
ID_QDEV,
ID_BLOCK,
ID_CHR,
ID_MAX /* last element, used as array size */
} IdSubSystems;

10
qom/qom-qmp-cmds.c
View File

@ -142,16 +142,6 @@ static ObjectPropertyInfo *make_device_property_info(ObjectClass *klass,
continue;
}
/*
* TODO Properties without a parser are just for dirty hacks.
* qdev_prop_ptr is the only such PropertyInfo. It's marked
* for removal. This conditional should be removed along with
* it.
*/
if (!prop->info->set && !prop->info->create) {
return NULL; /* no way to set it, don't show */
}
info = g_malloc0(sizeof(*info));
info->name = g_strdup(prop->name);
info->type = default_type ? g_strdup(default_type)

8
target/cris/cpu.c
View File

@ -147,6 +147,14 @@ static void cris_cpu_set_irq(void *opaque, int irq, int level)
CPUState *cs = CPU(cpu);
int type = irq == CRIS_CPU_IRQ ? CPU_INTERRUPT_HARD : CPU_INTERRUPT_NMI;
if (irq == CRIS_CPU_IRQ) {
/*
* The PIC passes us the vector for the IRQ as the value it sends
* over the qemu_irq line
*/
cpu->env.interrupt_vector = level;
}
if (level) {
cpu_interrupt(cs, type);
} else {

1
target/cris/cpu.h
View File

@ -34,6 +34,7 @@
#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
/* CRUS CPU device objects interrupt lines. */
/* PIC passes the vector for the IRQ as the value of it sends over qemu_irq */
#define CRIS_CPU_IRQ 0
#define CRIS_CPU_NMI 1

1
util/id.c
View File

@ -34,6 +34,7 @@ bool id_wellformed(const char *id)
static const char *const id_subsys_str[ID_MAX] = {
[ID_QDEV] = "qdev",
[ID_BLOCK] = "block",
[ID_CHR] = "chr",
};
/*