mirror of https://github.com/proxmox/mirror_qemu
target/hppa: Convert indexed memory insns
Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>master
Richard Henderson
parent
0c982a2817
commit
1cd012a5f7
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@ -26,6 +26,10 @@
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%sm_imm 16:10 !function=expand_sm_imm
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%im5_0 0:s1 1:4
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%im5_16 16:s1 17:4
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%ma_to_m 5:1 13:1 !function=ma_to_m
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####
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# Argument set definitions
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####
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@ -129,3 +133,23 @@ sub_tc 000010 ..... ..... .... 010011 0 ..... @rrr_cf
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sub_tsv_tc 000010 ..... ..... .... 110011 0 ..... @rrr_cf
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sub_b 000010 ..... ..... .... 010100 0 ..... @rrr_cf
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sub_b_tsv 000010 ..... ..... .... 110100 0 ..... @rrr_cf
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####
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# Index Mem
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####
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@ldstx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 &ldst disp=0
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@ldim5 ...... b:5 ..... sp:2 ......... t:5 \
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&ldst disp=%im5_16 x=0 scale=0 m=%ma_to_m
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@stim5 ...... b:5 t:5 sp:2 ......... ..... \
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&ldst disp=%im5_0 x=0 scale=0 m=%ma_to_m
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ld 000011 ..... ..... .. . 1 -- 00 size:2 ...... @ldim5
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ld 000011 ..... ..... .. . 0 -- 00 size:2 ...... @ldstx
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st 000011 ..... ..... .. . 1 -- 10 size:2 ...... @stim5
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ldc 000011 ..... ..... .. . 1 -- 0111 ...... @ldim5 size=2
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ldc 000011 ..... ..... .. . 0 -- 0111 ...... @ldstx size=2
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lda 000011 ..... ..... .. . 1 -- 0110 ...... @ldim5 size=2
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lda 000011 ..... ..... .. . 0 -- 0110 ...... @ldstx size=2
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sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 size=2
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stby 000011 b:5 r:5 sp:2 a:1 1 -- 1100 m:1 ..... disp=%im5_0
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@ -296,6 +296,13 @@ static int expand_sr3x(int val)
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return ~val;
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}
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/* Convert the M:A bits within a memory insn to the tri-state value
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we use for the final M. */
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static int ma_to_m(int val)
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{
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return val & 2 ? (val & 1 ? -1 : 1) : 0;
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}
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/* Include the auto-generated decoder. */
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#include "decode.inc.c"
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@ -1562,7 +1569,7 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb,
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#define do_store_reg do_store_32
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#endif
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static void do_load(DisasContext *ctx, unsigned rt, unsigned rb,
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static bool do_load(DisasContext *ctx, unsigned rt, unsigned rb,
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unsigned rx, int scale, target_sreg disp,
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unsigned sp, int modify, TCGMemOp mop)
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{
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@ -1580,7 +1587,7 @@ static void do_load(DisasContext *ctx, unsigned rt, unsigned rb,
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do_load_reg(ctx, dest, rb, rx, scale, disp, sp, modify, mop);
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save_gpr(ctx, rt, dest);
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nullify_end(ctx);
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return nullify_end(ctx);
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}
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static void do_floadw(DisasContext *ctx, unsigned rt, unsigned rb,
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@ -1623,13 +1630,13 @@ static void do_floadd(DisasContext *ctx, unsigned rt, unsigned rb,
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nullify_end(ctx);
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}
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static void do_store(DisasContext *ctx, unsigned rt, unsigned rb,
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static bool do_store(DisasContext *ctx, unsigned rt, unsigned rb,
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target_sreg disp, unsigned sp,
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int modify, TCGMemOp mop)
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{
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nullify_over(ctx);
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do_store_reg(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, sp, modify, mop);
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nullify_end(ctx);
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return nullify_end(ctx);
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}
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static void do_fstorew(DisasContext *ctx, unsigned rt, unsigned rb,
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@ -2831,119 +2838,57 @@ static bool trans_cmpiclr(DisasContext *ctx, uint32_t insn)
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return nullify_end(ctx);
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}
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static bool trans_ld_idx_i(DisasContext *ctx, uint32_t insn,
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const DisasInsn *di)
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static bool trans_ld(DisasContext *ctx, arg_ldst *a)
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{
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unsigned rt = extract32(insn, 0, 5);
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unsigned m = extract32(insn, 5, 1);
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unsigned sz = extract32(insn, 6, 2);
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unsigned a = extract32(insn, 13, 1);
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unsigned sp = extract32(insn, 14, 2);
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int disp = low_sextract(insn, 16, 5);
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unsigned rb = extract32(insn, 21, 5);
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int modify = (m ? (a ? -1 : 1) : 0);
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TCGMemOp mop = MO_TE | sz;
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do_load(ctx, rt, rb, 0, 0, disp, sp, modify, mop);
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return true;
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return do_load(ctx, a->t, a->b, a->x, a->scale ? a->size : 0,
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a->disp, a->sp, a->m, a->size | MO_TE);
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}
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static bool trans_ld_idx_x(DisasContext *ctx, uint32_t insn,
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const DisasInsn *di)
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static bool trans_st(DisasContext *ctx, arg_ldst *a)
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{
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unsigned rt = extract32(insn, 0, 5);
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unsigned m = extract32(insn, 5, 1);
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unsigned sz = extract32(insn, 6, 2);
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unsigned u = extract32(insn, 13, 1);
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unsigned sp = extract32(insn, 14, 2);
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unsigned rx = extract32(insn, 16, 5);
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unsigned rb = extract32(insn, 21, 5);
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TCGMemOp mop = MO_TE | sz;
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do_load(ctx, rt, rb, rx, u ? sz : 0, 0, sp, m, mop);
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return true;
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assert(a->x == 0 && a->scale == 0);
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return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size | MO_TE);
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}
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static bool trans_st_idx_i(DisasContext *ctx, uint32_t insn,
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const DisasInsn *di)
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static bool trans_ldc(DisasContext *ctx, arg_ldst *a)
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{
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int disp = low_sextract(insn, 0, 5);
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unsigned m = extract32(insn, 5, 1);
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unsigned sz = extract32(insn, 6, 2);
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unsigned a = extract32(insn, 13, 1);
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unsigned sp = extract32(insn, 14, 2);
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unsigned rr = extract32(insn, 16, 5);
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unsigned rb = extract32(insn, 21, 5);
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int modify = (m ? (a ? -1 : 1) : 0);
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TCGMemOp mop = MO_TE | sz;
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do_store(ctx, rr, rb, disp, sp, modify, mop);
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return true;
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}
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static bool trans_ldcw(DisasContext *ctx, uint32_t insn, const DisasInsn *di)
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{
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unsigned rt = extract32(insn, 0, 5);
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unsigned m = extract32(insn, 5, 1);
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unsigned i = extract32(insn, 12, 1);
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unsigned au = extract32(insn, 13, 1);
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unsigned sp = extract32(insn, 14, 2);
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unsigned rx = extract32(insn, 16, 5);
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unsigned rb = extract32(insn, 21, 5);
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TCGMemOp mop = MO_TEUL | MO_ALIGN_16;
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TCGMemOp mop = MO_TEUL | MO_ALIGN_16 | a->size;
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TCGv_reg zero, dest, ofs;
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TCGv_tl addr;
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int modify, disp = 0, scale = 0;
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nullify_over(ctx);
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if (i) {
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modify = (m ? (au ? -1 : 1) : 0);
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disp = low_sextract(rx, 0, 5);
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rx = 0;
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} else {
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modify = m;
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if (au) {
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scale = mop & MO_SIZE;
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}
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}
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if (modify) {
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if (a->m) {
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/* Base register modification. Make sure if RT == RB,
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we see the result of the load. */
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dest = get_temp(ctx);
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} else {
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dest = dest_gpr(ctx, rt);
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dest = dest_gpr(ctx, a->t);
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}
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form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
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ctx->mmu_idx == MMU_PHYS_IDX);
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form_gva(ctx, &addr, &ofs, a->b, a->x, a->scale ? a->size : 0,
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a->disp, a->sp, a->m, ctx->mmu_idx == MMU_PHYS_IDX);
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zero = tcg_const_reg(0);
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tcg_gen_atomic_xchg_reg(dest, addr, zero, ctx->mmu_idx, mop);
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if (modify) {
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save_gpr(ctx, rb, ofs);
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if (a->m) {
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save_gpr(ctx, a->b, ofs);
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}
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save_gpr(ctx, rt, dest);
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save_gpr(ctx, a->t, dest);
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return nullify_end(ctx);
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}
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static bool trans_stby(DisasContext *ctx, uint32_t insn, const DisasInsn *di)
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static bool trans_stby(DisasContext *ctx, arg_stby *a)
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{
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target_sreg disp = low_sextract(insn, 0, 5);
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unsigned m = extract32(insn, 5, 1);
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unsigned a = extract32(insn, 13, 1);
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unsigned sp = extract32(insn, 14, 2);
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unsigned rt = extract32(insn, 16, 5);
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unsigned rb = extract32(insn, 21, 5);
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TCGv_reg ofs, val;
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TCGv_tl addr;
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nullify_over(ctx);
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form_gva(ctx, &addr, &ofs, rb, 0, 0, disp, sp, m,
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form_gva(ctx, &addr, &ofs, a->b, 0, 0, a->disp, a->sp, a->m,
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ctx->mmu_idx == MMU_PHYS_IDX);
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val = load_gpr(ctx, rt);
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if (a) {
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val = load_gpr(ctx, a->r);
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if (a->a) {
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if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
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gen_helper_stby_e_parallel(cpu_env, addr, val);
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} else {
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@ -2956,75 +2901,36 @@ static bool trans_stby(DisasContext *ctx, uint32_t insn, const DisasInsn *di)
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gen_helper_stby_b(cpu_env, addr, val);
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}
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}
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if (m) {
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if (a->m) {
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tcg_gen_andi_reg(ofs, ofs, ~3);
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save_gpr(ctx, rb, ofs);
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save_gpr(ctx, a->b, ofs);
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}
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return nullify_end(ctx);
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}
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#ifndef CONFIG_USER_ONLY
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static bool trans_ldwa_idx_i(DisasContext *ctx, uint32_t insn,
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const DisasInsn *di)
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static bool trans_lda(DisasContext *ctx, arg_ldst *a)
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{
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int hold_mmu_idx = ctx->mmu_idx;
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CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
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/* ??? needs fixing for hppa64 -- ldda does not follow the same
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format wrt the sub-opcode in bits 6:9. */
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ctx->mmu_idx = MMU_PHYS_IDX;
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trans_ld_idx_i(ctx, insn, di);
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trans_ld(ctx, a);
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ctx->mmu_idx = hold_mmu_idx;
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return true;
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}
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static bool trans_ldwa_idx_x(DisasContext *ctx, uint32_t insn,
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const DisasInsn *di)
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static bool trans_sta(DisasContext *ctx, arg_ldst *a)
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{
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int hold_mmu_idx = ctx->mmu_idx;
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CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
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/* ??? needs fixing for hppa64 -- ldda does not follow the same
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format wrt the sub-opcode in bits 6:9. */
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ctx->mmu_idx = MMU_PHYS_IDX;
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trans_ld_idx_x(ctx, insn, di);
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trans_st(ctx, a);
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ctx->mmu_idx = hold_mmu_idx;
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return true;
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}
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static bool trans_stwa_idx_i(DisasContext *ctx, uint32_t insn,
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const DisasInsn *di)
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{
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int hold_mmu_idx = ctx->mmu_idx;
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CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
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/* ??? needs fixing for hppa64 -- ldda does not follow the same
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format wrt the sub-opcode in bits 6:9. */
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ctx->mmu_idx = MMU_PHYS_IDX;
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trans_st_idx_i(ctx, insn, di);
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ctx->mmu_idx = hold_mmu_idx;
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return true;
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}
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#endif
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static const DisasInsn table_index_mem[] = {
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{ 0x0c001000u, 0xfc001300, trans_ld_idx_i }, /* LD[BHWD], im */
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{ 0x0c000000u, 0xfc001300, trans_ld_idx_x }, /* LD[BHWD], rx */
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{ 0x0c001200u, 0xfc001300, trans_st_idx_i }, /* ST[BHWD] */
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{ 0x0c0001c0u, 0xfc0003c0, trans_ldcw },
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{ 0x0c001300u, 0xfc0013c0, trans_stby },
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#ifndef CONFIG_USER_ONLY
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{ 0x0c000180u, 0xfc00d3c0, trans_ldwa_idx_x }, /* LDWA, rx */
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{ 0x0c001180u, 0xfc00d3c0, trans_ldwa_idx_i }, /* LDWA, im */
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{ 0x0c001380u, 0xfc00d3c0, trans_stwa_idx_i }, /* STWA, im */
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#endif
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};
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static bool trans_ldil(DisasContext *ctx, uint32_t insn)
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{
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unsigned rt = extract32(insn, 21, 5);
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@ -4470,9 +4376,6 @@ static void translate_one(DisasContext *ctx, uint32_t insn)
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opc = extract32(insn, 26, 6);
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switch (opc) {
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case 0x03:
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translate_table(ctx, insn, table_index_mem);
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return;
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case 0x06:
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trans_fmpyadd(ctx, insn, false);
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return;
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