mirror of https://github.com/proxmox/mirror_qemu
target/ppc: Style fixes for translate_init.inc.c
Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org>master
David Gibson
parent
a65820908a
commit
1d28b5f6ef
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@ -41,12 +41,13 @@
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#include "fpu/softfloat.h"
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#include "qapi/qapi-commands-target.h"
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//#define PPC_DUMP_CPU
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//#define PPC_DEBUG_SPR
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//#define PPC_DUMP_SPR_ACCESSES
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/* #define PPC_DUMP_CPU */
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/* #define PPC_DEBUG_SPR */
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/* #define PPC_DUMP_SPR_ACCESSES */
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/* #define USE_APPLE_GDB */
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/* Generic callbacks:
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/*
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* Generic callbacks:
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* do nothing but store/retrieve spr value
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*/
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static void spr_load_dump_spr(int sprn)
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@ -58,7 +59,7 @@ static void spr_load_dump_spr(int sprn)
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#endif
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}
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static void spr_read_generic (DisasContext *ctx, int gprn, int sprn)
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static void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
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{
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gen_load_spr(cpu_gpr[gprn], sprn);
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spr_load_dump_spr(sprn);
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@ -230,13 +231,13 @@ static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
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}
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}
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__attribute__ (( unused ))
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ATTRIBUTE_UNUSED
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static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
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{
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gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
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}
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__attribute__ (( unused ))
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ATTRIBUTE_UNUSED
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static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
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{
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gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
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@ -267,20 +268,20 @@ static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
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}
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}
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__attribute__ (( unused ))
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ATTRIBUTE_UNUSED
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static void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
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{
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gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
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}
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__attribute__ (( unused ))
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ATTRIBUTE_UNUSED
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static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
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{
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gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
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}
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#if defined(TARGET_PPC64)
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__attribute__ (( unused ))
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ATTRIBUTE_UNUSED
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static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
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{
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gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
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@ -319,12 +320,16 @@ static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
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/* IBAT0L...IBAT7L */
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static void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
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{
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tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
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tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
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offsetof(CPUPPCState,
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IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
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}
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static void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
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{
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tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
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tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
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offsetof(CPUPPCState,
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IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
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}
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static void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
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@ -359,12 +364,16 @@ static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
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/* DBAT0L...DBAT7L */
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static void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
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{
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tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
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tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
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offsetof(CPUPPCState,
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DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
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}
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static void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
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{
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tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
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tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
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offsetof(CPUPPCState,
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DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
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}
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static void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
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@ -473,7 +482,9 @@ static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
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#if !defined(CONFIG_USER_ONLY)
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static void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn)
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{
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tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
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tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
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offsetof(CPUPPCState,
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IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
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}
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static void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn)
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@ -532,7 +543,8 @@ static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
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#if !defined(CONFIG_USER_ONLY)
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static void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
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{
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tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
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tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
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offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
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}
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static void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
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@ -661,14 +673,20 @@ static inline void vscr_init(CPUPPCState *env, uint32_t val)
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static inline void _spr_register(CPUPPCState *env, int num,
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const char *name,
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void (*uea_read)(DisasContext *ctx, int gprn, int sprn),
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void (*uea_write)(DisasContext *ctx, int sprn, int gprn),
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void (*uea_read)(DisasContext *ctx,
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int gprn, int sprn),
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void (*uea_write)(DisasContext *ctx,
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int sprn, int gprn),
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#if !defined(CONFIG_USER_ONLY)
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void (*oea_read)(DisasContext *ctx, int gprn, int sprn),
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void (*oea_write)(DisasContext *ctx, int sprn, int gprn),
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void (*hea_read)(DisasContext *opaque, int gprn, int sprn),
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void (*hea_write)(DisasContext *opaque, int sprn, int gprn),
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void (*oea_read)(DisasContext *ctx,
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int gprn, int sprn),
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void (*oea_write)(DisasContext *ctx,
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int sprn, int gprn),
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void (*hea_read)(DisasContext *opaque,
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int gprn, int sprn),
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void (*hea_write)(DisasContext *opaque,
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int sprn, int gprn),
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#endif
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#if defined(CONFIG_KVM)
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uint64_t one_reg_id,
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@ -678,7 +696,7 @@ static inline void _spr_register(CPUPPCState *env, int num,
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ppc_spr_t *spr;
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spr = &env->spr_cb[num];
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if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
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if (spr->name != NULL || env->spr[num] != 0x00000000 ||
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#if !defined(CONFIG_USER_ONLY)
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spr->oea_read != NULL || spr->oea_write != NULL ||
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#endif
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@ -774,8 +792,10 @@ static void gen_spr_sdr1(CPUPPCState *env)
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{
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#ifndef CONFIG_USER_ONLY
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if (env->has_hv_mode) {
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/* SDR1 is a hypervisor resource on CPUs which have a
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* hypervisor mode */
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/*
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* SDR1 is a hypervisor resource on CPUs which have a
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* hypervisor mode
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*/
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spr_register_hv(env, SPR_SDR1, "SDR1",
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SPR_NOACCESS, SPR_NOACCESS,
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SPR_NOACCESS, SPR_NOACCESS,
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@ -1123,7 +1143,8 @@ static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
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TCGv t1 = tcg_temp_new();
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TCGv t2 = tcg_temp_new();
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/* Note, the HV=1 PR=0 case is handled earlier by simply using
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/*
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* Note, the HV=1 PR=0 case is handled earlier by simply using
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* spr_write_generic for HV mode in the SPR table
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*/
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@ -1157,7 +1178,8 @@ static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
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TCGv t1 = tcg_temp_new();
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TCGv t2 = tcg_temp_new();
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/* Note, the HV=1 case is handled earlier by simply using
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/*
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* Note, the HV=1 case is handled earlier by simply using
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* spr_write_generic for HV mode in the SPR table
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*/
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@ -1187,7 +1209,8 @@ static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
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TCGv t1 = tcg_temp_new();
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TCGv t2 = tcg_temp_new();
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/* Note, the HV=1 case is handled earlier by simply using
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/*
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* Note, the HV=1 case is handled earlier by simply using
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* spr_write_generic for HV mode in the SPR table
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*/
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@ -1215,10 +1238,13 @@ static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
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static void gen_spr_amr(CPUPPCState *env)
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{
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#ifndef CONFIG_USER_ONLY
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/* Virtual Page Class Key protection */
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/* The AMR is accessible either via SPR 13 or SPR 29. 13 is
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/*
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* Virtual Page Class Key protection
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*
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* The AMR is accessible either via SPR 13 or SPR 29. 13 is
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* userspace accessible, 29 is privileged. So we only need to set
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* the kvm ONE_REG id on one of them, we use 29 */
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* the kvm ONE_REG id on one of them, we use 29
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*/
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spr_register(env, SPR_UAMR, "UAMR",
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&spr_read_generic, &spr_write_amr,
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&spr_read_generic, &spr_write_amr,
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@ -1902,7 +1928,8 @@ static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
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/* TLB assist registers */
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/* XXX : not implemented */
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for (i = 0; i < 8; i++) {
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void (*uea_write)(DisasContext *ctx, int sprn, int gprn) = &spr_write_generic32;
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void (*uea_write)(DisasContext *ctx, int sprn, int gprn) =
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&spr_write_generic32;
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if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
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uea_write = &spr_write_generic;
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}
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@ -2798,7 +2825,6 @@ static void gen_spr_8xx(CPUPPCState *env)
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0x00000000);
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}
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// XXX: TODO
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/*
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* AMR => SPR 29 (Power 2.04)
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* CTRL => SPR 136 (Power 2.04)
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@ -3344,16 +3370,18 @@ static int check_pow_nocheck(CPUPPCState *env)
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static int check_pow_hid0(CPUPPCState *env)
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{
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if (env->spr[SPR_HID0] & 0x00E00000)
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if (env->spr[SPR_HID0] & 0x00E00000) {
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return 1;
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}
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return 0;
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}
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static int check_pow_hid0_74xx(CPUPPCState *env)
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{
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if (env->spr[SPR_HID0] & 0x00600000)
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if (env->spr[SPR_HID0] & 0x00600000) {
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return 1;
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}
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return 0;
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}
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@ -4602,7 +4630,8 @@ POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
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dc->desc = "e200 core";
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pcc->init_proc = init_proc_e200;
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pcc->check_pow = check_pow_hid0;
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/* XXX: unimplemented instructions:
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/*
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* XXX: unimplemented instructions:
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* dcblc
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* dcbtlst
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* dcbtstls
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@ -4797,18 +4826,18 @@ static void init_proc_e500(CPUPPCState *env, int version)
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* gen_spr_BookE(env, 0x0000000F0000FD7FULL);
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*/
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switch (version) {
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case fsl_e500v1:
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case fsl_e500v2:
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default:
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ivor_mask = 0x0000000F0000FFFFULL;
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break;
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case fsl_e500mc:
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case fsl_e5500:
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ivor_mask = 0x000003FE0000FFFFULL;
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break;
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case fsl_e6500:
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ivor_mask = 0x000003FF0000FFFFULL;
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break;
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case fsl_e500v1:
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case fsl_e500v2:
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default:
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ivor_mask = 0x0000000F0000FFFFULL;
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break;
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case fsl_e500mc:
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case fsl_e5500:
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ivor_mask = 0x000003FE0000FFFFULL;
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break;
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case fsl_e6500:
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ivor_mask = 0x000003FF0000FFFFULL;
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break;
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}
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gen_spr_BookE(env, ivor_mask);
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gen_spr_usprg3(env);
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@ -4848,7 +4877,8 @@ static void init_proc_e500(CPUPPCState *env, int version)
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tlbncfg[1] = 0x40028040;
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break;
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default:
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cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
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cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n",
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env->spr[SPR_PVR]);
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}
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#endif
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/* Cache sizes */
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@ -4872,7 +4902,8 @@ static void init_proc_e500(CPUPPCState *env, int version)
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l1cfg1 |= 0x0B83820;
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break;
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default:
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cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
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cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n",
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env->spr[SPR_PVR]);
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}
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gen_spr_BookE206(env, 0x000000DF, tlbncfg, mmucfg);
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/* XXX : not implemented */
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@ -5252,7 +5283,8 @@ static void init_proc_601(CPUPPCState *env)
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0x00000000);
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/* Memory management */
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init_excp_601(env);
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/* XXX: beware that dcache line size is 64
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/*
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* XXX: beware that dcache line size is 64
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* but dcbz uses 32 bytes "sectors"
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* XXX: this breaks clcs instruction !
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*/
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@ -5789,7 +5821,8 @@ static void init_proc_750(CPUPPCState *env)
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0x00000000);
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/* Memory management */
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gen_low_BATs(env);
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/* XXX: high BATs are also present but are known to be bugged on
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/*
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* XXX: high BATs are also present but are known to be bugged on
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* die version 1.x
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*/
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init_excp_7x0(env);
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@ -5971,7 +6004,8 @@ POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
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dc->desc = "PowerPC 750 CL";
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pcc->init_proc = init_proc_750cl;
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pcc->check_pow = check_pow_hid0;
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/* XXX: not implemented:
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/*
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* XXX: not implemented:
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* cache lock instructions:
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* dcbz_l
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* floating point paired instructions
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@ -7569,8 +7603,10 @@ static void gen_spr_book3s_altivec(CPUPPCState *env)
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&spr_read_generic, &spr_write_generic,
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KVM_REG_PPC_VRSAVE, 0x00000000);
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/* Can't find information on what this should be on reset. This
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* value is the one used by 74xx processors. */
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/*
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* Can't find information on what this should be on reset. This
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* value is the one used by 74xx processors.
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*/
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vscr_init(env, 0x00010000);
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}
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@ -8975,8 +9011,9 @@ static void init_ppc_proc(PowerPCCPU *cpu)
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env->irq_inputs = NULL;
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/* Set all exception vectors to an invalid address */
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for (i = 0; i < POWERPC_EXCP_NB; i++)
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for (i = 0; i < POWERPC_EXCP_NB; i++) {
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env->excp_vectors[i] = (target_ulong)(-1ULL);
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}
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env->ivor_mask = 0x00000000;
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env->ivpr_mask = 0x00000000;
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/* Default MMU definitions */
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@ -9108,8 +9145,9 @@ static void init_ppc_proc(PowerPCCPU *cpu)
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#if !defined(CONFIG_USER_ONLY)
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if (env->nb_tlb != 0) {
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int nb_tlb = env->nb_tlb;
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if (env->id_tlbs != 0)
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if (env->id_tlbs != 0) {
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nb_tlb *= 2;
|
||||
}
|
||||
switch (env->tlb_type) {
|
||||
case TLB_6XX:
|
||||
env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb);
|
||||
|
|
@ -9201,8 +9239,9 @@ static void fill_new_table(opc_handler_t **table, int len)
|
|||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < len; i++)
|
||||
for (i = 0; i < len; i++) {
|
||||
table[i] = &invalid_handler;
|
||||
}
|
||||
}
|
||||
|
||||
static int create_new_table(opc_handler_t **table, unsigned char idx)
|
||||
|
|
@ -9219,8 +9258,9 @@ static int create_new_table(opc_handler_t **table, unsigned char idx)
|
|||
static int insert_in_table(opc_handler_t **table, unsigned char idx,
|
||||
opc_handler_t *handler)
|
||||
{
|
||||
if (table[idx] != &invalid_handler)
|
||||
if (table[idx] != &invalid_handler) {
|
||||
return -1;
|
||||
}
|
||||
table[idx] = handler;
|
||||
|
||||
return 0;
|
||||
|
|
@ -9341,17 +9381,20 @@ static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn)
|
|||
}
|
||||
} else {
|
||||
if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
|
||||
insn->opc3, &insn->handler) < 0)
|
||||
insn->opc3, &insn->handler) < 0) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
if (register_ind_insn(ppc_opcodes, insn->opc1,
|
||||
insn->opc2, &insn->handler) < 0)
|
||||
insn->opc2, &insn->handler) < 0) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
|
||||
if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -9363,8 +9406,9 @@ static int test_opcode_table(opc_handler_t **table, int len)
|
|||
|
||||
for (i = 0, count = 0; i < len; i++) {
|
||||
/* Consistency fixup */
|
||||
if (table[i] == NULL)
|
||||
if (table[i] == NULL) {
|
||||
table[i] = &invalid_handler;
|
||||
}
|
||||
if (table[i] != &invalid_handler) {
|
||||
if (is_indirect_opcode(table[i])) {
|
||||
tmp = test_opcode_table(ind_table(table[i]),
|
||||
|
|
@ -9386,8 +9430,9 @@ static int test_opcode_table(opc_handler_t **table, int len)
|
|||
|
||||
static void fix_opcode_tables(opc_handler_t **ppc_opcodes)
|
||||
{
|
||||
if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0)
|
||||
if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) {
|
||||
printf("*** WARNING: no opcode defined !\n");
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
|
|
@ -9726,14 +9771,15 @@ static int ppc_fixup_cpu(PowerPCCPU *cpu)
|
|||
{
|
||||
CPUPPCState *env = &cpu->env;
|
||||
|
||||
/* TCG doesn't (yet) emulate some groups of instructions that
|
||||
* are implemented on some otherwise supported CPUs (e.g. VSX
|
||||
* and decimal floating point instructions on POWER7). We
|
||||
* remove unsupported instruction groups from the cpu state's
|
||||
* instruction masks and hope the guest can cope. For at
|
||||
* least the pseries machine, the unavailability of these
|
||||
* instructions can be advertised to the guest via the device
|
||||
* tree. */
|
||||
/*
|
||||
* TCG doesn't (yet) emulate some groups of instructions that are
|
||||
* implemented on some otherwise supported CPUs (e.g. VSX and
|
||||
* decimal floating point instructions on POWER7). We remove
|
||||
* unsupported instruction groups from the cpu state's instruction
|
||||
* masks and hope the guest can cope. For at least the pseries
|
||||
* machine, the unavailability of these instructions can be
|
||||
* advertised to the guest via the device tree.
|
||||
*/
|
||||
if ((env->insns_flags & ~PPC_TCG_INSNS)
|
||||
|| (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
|
||||
warn_report("Disabling some instructions which are not "
|
||||
|
|
@ -9928,31 +9974,37 @@ static void ppc_cpu_realize(DeviceState *dev, Error **errp)
|
|||
" Bus model : %s\n",
|
||||
excp_model, bus_model);
|
||||
printf(" MSR features :\n");
|
||||
if (env->flags & POWERPC_FLAG_SPE)
|
||||
if (env->flags & POWERPC_FLAG_SPE) {
|
||||
printf(" signal processing engine enable"
|
||||
"\n");
|
||||
else if (env->flags & POWERPC_FLAG_VRE)
|
||||
} else if (env->flags & POWERPC_FLAG_VRE) {
|
||||
printf(" vector processor enable\n");
|
||||
if (env->flags & POWERPC_FLAG_TGPR)
|
||||
}
|
||||
if (env->flags & POWERPC_FLAG_TGPR) {
|
||||
printf(" temporary GPRs\n");
|
||||
else if (env->flags & POWERPC_FLAG_CE)
|
||||
} else if (env->flags & POWERPC_FLAG_CE) {
|
||||
printf(" critical input enable\n");
|
||||
if (env->flags & POWERPC_FLAG_SE)
|
||||
}
|
||||
if (env->flags & POWERPC_FLAG_SE) {
|
||||
printf(" single-step trace mode\n");
|
||||
else if (env->flags & POWERPC_FLAG_DWE)
|
||||
} else if (env->flags & POWERPC_FLAG_DWE) {
|
||||
printf(" debug wait enable\n");
|
||||
else if (env->flags & POWERPC_FLAG_UBLE)
|
||||
} else if (env->flags & POWERPC_FLAG_UBLE) {
|
||||
printf(" user BTB lock enable\n");
|
||||
if (env->flags & POWERPC_FLAG_BE)
|
||||
}
|
||||
if (env->flags & POWERPC_FLAG_BE) {
|
||||
printf(" branch-step trace mode\n");
|
||||
else if (env->flags & POWERPC_FLAG_DE)
|
||||
} else if (env->flags & POWERPC_FLAG_DE) {
|
||||
printf(" debug interrupt enable\n");
|
||||
if (env->flags & POWERPC_FLAG_PX)
|
||||
}
|
||||
if (env->flags & POWERPC_FLAG_PX) {
|
||||
printf(" inclusive protection\n");
|
||||
else if (env->flags & POWERPC_FLAG_PMM)
|
||||
} else if (env->flags & POWERPC_FLAG_PMM) {
|
||||
printf(" performance monitor mark\n");
|
||||
if (env->flags == POWERPC_FLAG_NONE)
|
||||
}
|
||||
if (env->flags == POWERPC_FLAG_NONE) {
|
||||
printf(" none\n");
|
||||
}
|
||||
printf(" Time-base/decrementer clock source: %s\n",
|
||||
env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
|
||||
dump_ppc_insns(env);
|
||||
|
|
@ -10094,8 +10146,9 @@ static ObjectClass *ppc_cpu_class_by_name(const char *name)
|
|||
const char *p;
|
||||
unsigned long pvr;
|
||||
|
||||
/* Lookup by PVR if cpu_model is valid 8 digit hex number
|
||||
* (excl: 0x prefix if present)
|
||||
/*
|
||||
* Lookup by PVR if cpu_model is valid 8 digit hex number (excl:
|
||||
* 0x prefix if present)
|
||||
*/
|
||||
if (!qemu_strtoul(name, &p, 16, &pvr)) {
|
||||
int len = p - name;
|
||||
|
|
@ -10439,14 +10492,14 @@ static void ppc_cpu_instance_init(Object *obj)
|
|||
env->bfd_mach = pcc->bfd_mach;
|
||||
env->check_pow = pcc->check_pow;
|
||||
|
||||
/* Mark HV mode as supported if the CPU has an MSR_HV bit
|
||||
* in the msr_mask. The mask can later be cleared by PAPR
|
||||
* mode but the hv mode support will remain, thus enforcing
|
||||
* that we cannot use priv. instructions in guest in PAPR
|
||||
* mode. For 970 we currently simply don't set HV in msr_mask
|
||||
* thus simulating an "Apple mode" 970. If we ever want to
|
||||
* support 970 HV mode, we'll have to add a processor attribute
|
||||
* of some sort.
|
||||
/*
|
||||
* Mark HV mode as supported if the CPU has an MSR_HV bit in the
|
||||
* msr_mask. The mask can later be cleared by PAPR mode but the hv
|
||||
* mode support will remain, thus enforcing that we cannot use
|
||||
* priv. instructions in guest in PAPR mode. For 970 we currently
|
||||
* simply don't set HV in msr_mask thus simulating an "Apple mode"
|
||||
* 970. If we ever want to support 970 HV mode, we'll have to add
|
||||
* a processor attribute of some sort.
|
||||
*/
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
|
||||
|
|
@ -10573,7 +10626,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
|
|||
cc->tcg_initialize = ppc_translate_init;
|
||||
#endif
|
||||
cc->disas_set_info = ppc_disas_set_info;
|
||||
|
||||
|
||||
dc->fw_name = "PowerPC,UNKNOWN";
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue