mirror of https://github.com/proxmox/mirror_qemu
hw/timer: Add value matching support to aspeed_timer
Value matching allows Linux to boot with CONFIG_NO_HZ_IDLE=y on the palmetto-bmc machine. Two match registers are provided for each timer. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1465974248-20434-1-git-send-email-andrew@aj.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>master
Andrew Jeffery
Peter Maydell
parent
3b1a222501
commit
1d3e65aa7a
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@ -10,12 +10,10 @@
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*/
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#include "qemu/osdep.h"
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#include "hw/ptimer.h"
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#include "hw/sysbus.h"
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#include "hw/timer/aspeed_timer.h"
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#include "qemu-common.h"
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#include "qemu/bitops.h"
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#include "qemu/main-loop.h"
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#include "qemu/timer.h"
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#include "qemu/log.h"
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#include "trace.h"
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@ -77,21 +75,96 @@ static inline bool timer_can_pulse(AspeedTimer *t)
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return t->id >= TIMER_FIRST_CAP_PULSE;
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}
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static inline bool timer_external_clock(AspeedTimer *t)
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{
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return timer_ctrl_status(t, op_external_clock);
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}
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static uint32_t clock_rates[] = { TIMER_CLOCK_APB_HZ, TIMER_CLOCK_EXT_HZ };
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static inline uint32_t calculate_rate(struct AspeedTimer *t)
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{
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return clock_rates[timer_external_clock(t)];
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}
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static inline uint32_t calculate_ticks(struct AspeedTimer *t, uint64_t now_ns)
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{
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uint64_t delta_ns = now_ns - MIN(now_ns, t->start);
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uint32_t rate = calculate_rate(t);
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uint64_t ticks = muldiv64(delta_ns, rate, NANOSECONDS_PER_SECOND);
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return t->reload - MIN(t->reload, ticks);
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}
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static inline uint64_t calculate_time(struct AspeedTimer *t, uint32_t ticks)
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{
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uint64_t delta_ns;
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uint64_t delta_ticks;
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delta_ticks = t->reload - MIN(t->reload, ticks);
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delta_ns = muldiv64(delta_ticks, NANOSECONDS_PER_SECOND, calculate_rate(t));
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return t->start + delta_ns;
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}
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static uint64_t calculate_next(struct AspeedTimer *t)
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{
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uint64_t next = 0;
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uint32_t rate = calculate_rate(t);
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while (!next) {
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/* We don't know the relationship between the values in the match
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* registers, so sort using MAX/MIN/zero. We sort in that order as the
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* timer counts down to zero. */
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uint64_t seq[] = {
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calculate_time(t, MAX(t->match[0], t->match[1])),
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calculate_time(t, MIN(t->match[0], t->match[1])),
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calculate_time(t, 0),
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};
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uint64_t reload_ns;
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uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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if (now < seq[0]) {
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next = seq[0];
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} else if (now < seq[1]) {
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next = seq[1];
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} else if (now < seq[2]) {
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next = seq[2];
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} else {
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reload_ns = muldiv64(t->reload, NANOSECONDS_PER_SECOND, rate);
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t->start = now - ((now - t->start) % reload_ns);
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}
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}
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return next;
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}
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static void aspeed_timer_expire(void *opaque)
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{
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AspeedTimer *t = opaque;
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bool interrupt = false;
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uint32_t ticks;
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/* Only support interrupts on match values of zero for the moment - this is
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* sufficient to boot an aspeed_defconfig Linux kernel.
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*
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* TODO: matching on arbitrary values (see e.g. hw/timer/a9gtimer.c)
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*/
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bool match = !(t->match[0] && t->match[1]);
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bool interrupt = timer_overflow_interrupt(t) || match;
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if (timer_enabled(t) && interrupt) {
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if (!timer_enabled(t)) {
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return;
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}
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ticks = calculate_ticks(t, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
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if (!ticks) {
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interrupt = timer_overflow_interrupt(t) || !t->match[0] || !t->match[1];
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} else if (ticks <= MIN(t->match[0], t->match[1])) {
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interrupt = true;
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} else if (ticks <= MAX(t->match[0], t->match[1])) {
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interrupt = true;
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}
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if (interrupt) {
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t->level = !t->level;
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qemu_set_irq(t->irq, t->level);
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}
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timer_mod(&t->timer, calculate_next(t));
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}
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static uint64_t aspeed_timer_get_value(AspeedTimer *t, int reg)
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@ -100,7 +173,7 @@ static uint64_t aspeed_timer_get_value(AspeedTimer *t, int reg)
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switch (reg) {
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case TIMER_REG_STATUS:
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value = ptimer_get_count(t->timer);
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value = calculate_ticks(t, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
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break;
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case TIMER_REG_RELOAD:
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value = t->reload;
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@ -160,24 +233,22 @@ static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg,
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switch (reg) {
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case TIMER_REG_STATUS:
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if (timer_enabled(t)) {
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ptimer_set_count(t->timer, value);
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uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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int64_t delta = (int64_t) value - (int64_t) calculate_ticks(t, now);
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uint32_t rate = calculate_rate(t);
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t->start += muldiv64(delta, NANOSECONDS_PER_SECOND, rate);
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timer_mod(&t->timer, calculate_next(t));
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}
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break;
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case TIMER_REG_RELOAD:
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t->reload = value;
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ptimer_set_limit(t->timer, value, 1);
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break;
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case TIMER_REG_MATCH_FIRST:
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case TIMER_REG_MATCH_SECOND:
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if (value) {
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/* Non-zero match values are unsupported. As such an interrupt will
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* always be triggered when the timer reaches zero even if the
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* overflow interrupt control bit is clear.
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*/
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qemu_log_mask(LOG_UNIMP, "%s: Match value unsupported by device: "
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"0x%" PRIx32 "\n", __func__, value);
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} else {
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t->match[reg - 2] = value;
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t->match[reg - 2] = value;
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if (timer_enabled(t)) {
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timer_mod(&t->timer, calculate_next(t));
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}
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break;
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default:
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@ -196,21 +267,16 @@ static void aspeed_timer_ctrl_enable(AspeedTimer *t, bool enable)
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{
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trace_aspeed_timer_ctrl_enable(t->id, enable);
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if (enable) {
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ptimer_run(t->timer, 0);
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t->start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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timer_mod(&t->timer, calculate_next(t));
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} else {
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ptimer_stop(t->timer);
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ptimer_set_limit(t->timer, t->reload, 1);
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timer_del(&t->timer);
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}
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}
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static void aspeed_timer_ctrl_external_clock(AspeedTimer *t, bool enable)
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{
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trace_aspeed_timer_ctrl_external_clock(t->id, enable);
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if (enable) {
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ptimer_set_freq(t->timer, TIMER_CLOCK_EXT_HZ);
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} else {
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ptimer_set_freq(t->timer, TIMER_CLOCK_APB_HZ);
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}
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}
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static void aspeed_timer_ctrl_overflow_interrupt(AspeedTimer *t, bool enable)
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@ -351,12 +417,10 @@ static const MemoryRegionOps aspeed_timer_ops = {
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static void aspeed_init_one_timer(AspeedTimerCtrlState *s, uint8_t id)
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{
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QEMUBH *bh;
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AspeedTimer *t = &s->timers[id];
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t->id = id;
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bh = qemu_bh_new(aspeed_timer_expire, t);
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t->timer = ptimer_init(bh);
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timer_init_ns(&t->timer, QEMU_CLOCK_VIRTUAL, aspeed_timer_expire, t);
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}
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static void aspeed_timer_realize(DeviceState *dev, Error **errp)
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@ -399,12 +463,12 @@ static void aspeed_timer_reset(DeviceState *dev)
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static const VMStateDescription vmstate_aspeed_timer = {
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.name = "aspeed.timer",
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.version_id = 1,
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.minimum_version_id = 1,
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.version_id = 2,
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.minimum_version_id = 2,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(id, AspeedTimer),
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VMSTATE_INT32(level, AspeedTimer),
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VMSTATE_PTIMER(timer, AspeedTimer),
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VMSTATE_TIMER(timer, AspeedTimer),
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VMSTATE_UINT32(reload, AspeedTimer),
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VMSTATE_UINT32_ARRAY(match, AspeedTimer, 2),
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VMSTATE_END_OF_LIST()
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@ -419,7 +483,7 @@ static const VMStateDescription vmstate_aspeed_timer_state = {
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VMSTATE_UINT32(ctrl, AspeedTimerCtrlState),
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VMSTATE_UINT32(ctrl2, AspeedTimerCtrlState),
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VMSTATE_STRUCT_ARRAY(timers, AspeedTimerCtrlState,
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ASPEED_TIMER_NR_TIMERS, 1, vmstate_aspeed_timer,
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ASPEED_TIMER_NR_TIMERS, 2, vmstate_aspeed_timer,
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AspeedTimer),
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VMSTATE_END_OF_LIST()
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}
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@ -22,7 +22,7 @@
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#ifndef ASPEED_TIMER_H
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#define ASPEED_TIMER_H
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#include "hw/ptimer.h"
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#include "qemu/timer.h"
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#define ASPEED_TIMER(obj) \
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OBJECT_CHECK(AspeedTimerCtrlState, (obj), TYPE_ASPEED_TIMER);
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@ -33,15 +33,16 @@ typedef struct AspeedTimer {
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qemu_irq irq;
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uint8_t id;
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QEMUTimer timer;
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/**
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* Track the line level as the ASPEED timers implement edge triggered
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* interrupts, signalling with both the rising and falling edge.
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*/
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int32_t level;
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ptimer_state *timer;
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uint32_t reload;
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uint32_t match[2];
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uint64_t start;
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} AspeedTimer;
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typedef struct AspeedTimerCtrlState {
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