mirror of https://github.com/proxmox/mirror_qemu
target/ppc: add LPCR[HR] to DisasContext and hflags
Add a Host Radix field (hr) in DisasContext with LPCR[HR] value to allow us to decide between Radix and HPT while validating instructions arguments. Note that PowerISA v3.1 does not require LPCR[HR] and PATE.HR to match if the thread is in ultravisor/hypervisor real addressing mode, so ctx->hr may be invalid if ctx->hv and ctx->dr are set. Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20210917114751.206845-2-matheus.ferst@eldorado.org.br> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>master
parent
7279810b67
commit
1db3632a14
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@ -600,6 +600,7 @@ enum {
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HFLAGS_64 = 2, /* computed from MSR_CE and MSR_SF */
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HFLAGS_GTSE = 3, /* computed from SPR_LPCR[GTSE] */
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HFLAGS_DR = 4, /* MSR_DR */
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HFLAGS_HR = 5, /* computed from SPR_LPCR[HR] */
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HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */
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HFLAGS_TM = 8, /* computed from MSR_TM */
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HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */
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@ -106,6 +106,9 @@ static uint32_t hreg_compute_hflags_value(CPUPPCState *env)
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if (env->spr[SPR_LPCR] & LPCR_GTSE) {
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hflags |= 1 << HFLAGS_GTSE;
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}
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if (env->spr[SPR_LPCR] & LPCR_HR) {
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hflags |= 1 << HFLAGS_HR;
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}
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#ifndef CONFIG_USER_ONLY
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if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) {
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@ -175,6 +175,7 @@ struct DisasContext {
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bool spe_enabled;
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bool tm_enabled;
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bool gtse;
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bool hr;
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ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
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int singlestep_enabled;
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uint32_t flags;
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@ -8539,6 +8540,7 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1;
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ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1;
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ctx->gtse = (hflags >> HFLAGS_GTSE) & 1;
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ctx->hr = (hflags >> HFLAGS_HR) & 1;
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ctx->singlestep_enabled = 0;
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if ((hflags >> HFLAGS_SE) & 1) {
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