mirror of https://github.com/proxmox/mirror_qemu
exec: introduce MemoryRegionCache
Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>master
Paolo Bonzini
parent
715c31ec8e
commit
1f4e496e1f
76
exec.c
76
exec.c
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@ -3077,6 +3077,82 @@ void cpu_physical_memory_unmap(void *buffer, hwaddr len,
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#define RCU_READ_UNLOCK(...) rcu_read_unlock()
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#include "memory_ldst.inc.c"
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int64_t address_space_cache_init(MemoryRegionCache *cache,
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AddressSpace *as,
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hwaddr addr,
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hwaddr len,
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bool is_write)
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{
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hwaddr l, xlat;
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MemoryRegion *mr;
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void *ptr;
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assert(len > 0);
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l = len;
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mr = address_space_translate(as, addr, &xlat, &l, is_write);
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if (!memory_access_is_direct(mr, is_write)) {
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return -EINVAL;
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}
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l = address_space_extend_translation(as, addr, len, mr, xlat, l, is_write);
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ptr = qemu_ram_ptr_length(mr->ram_block, xlat, &l);
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cache->xlat = xlat;
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cache->is_write = is_write;
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cache->mr = mr;
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cache->ptr = ptr;
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cache->len = l;
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memory_region_ref(cache->mr);
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return l;
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}
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void address_space_cache_invalidate(MemoryRegionCache *cache,
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hwaddr addr,
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hwaddr access_len)
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{
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assert(cache->is_write);
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invalidate_and_set_dirty(cache->mr, addr + cache->xlat, access_len);
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}
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void address_space_cache_destroy(MemoryRegionCache *cache)
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{
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if (!cache->mr) {
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return;
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}
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if (xen_enabled()) {
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xen_invalidate_map_cache_entry(cache->ptr);
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}
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memory_region_unref(cache->mr);
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}
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/* Called from RCU critical section. This function has the same
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* semantics as address_space_translate, but it only works on a
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* predefined range of a MemoryRegion that was mapped with
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* address_space_cache_init.
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*/
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static inline MemoryRegion *address_space_translate_cached(
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MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat,
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hwaddr *plen, bool is_write)
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{
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assert(addr < cache->len && *plen <= cache->len - addr);
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*xlat = addr + cache->xlat;
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return cache->mr;
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}
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#define ARG1_DECL MemoryRegionCache *cache
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#define ARG1 cache
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#define SUFFIX _cached
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#define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__)
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#define IS_DIRECT(mr, is_write) true
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#define MAP_RAM(mr, ofs) (cache->ptr + (ofs - cache->xlat))
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#define INVALIDATE(mr, ofs, len) ((void)0)
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#define RCU_READ_LOCK() ((void)0)
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#define RCU_READ_UNLOCK() ((void)0)
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#include "memory_ldst.inc.c"
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/* virtual memory access for debug (includes writing to ROM) */
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int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
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uint8_t *buf, int len, int is_write)
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@ -186,6 +186,29 @@ void address_space_stl(AddressSpace *as, hwaddr addr, uint32_t val,
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MemTxAttrs attrs, MemTxResult *result);
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void address_space_stq(AddressSpace *as, hwaddr addr, uint64_t val,
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MemTxAttrs attrs, MemTxResult *result);
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uint32_t lduw_phys_cached(MemoryRegionCache *cache, hwaddr addr);
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uint32_t ldl_phys_cached(MemoryRegionCache *cache, hwaddr addr);
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uint64_t ldq_phys_cached(MemoryRegionCache *cache, hwaddr addr);
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void stl_phys_notdirty_cached(MemoryRegionCache *cache, hwaddr addr, uint32_t val);
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void stw_phys_cached(MemoryRegionCache *cache, hwaddr addr, uint32_t val);
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void stl_phys_cached(MemoryRegionCache *cache, hwaddr addr, uint32_t val);
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void stq_phys_cached(MemoryRegionCache *cache, hwaddr addr, uint64_t val);
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uint32_t address_space_lduw_cached(MemoryRegionCache *cache, hwaddr addr,
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MemTxAttrs attrs, MemTxResult *result);
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uint32_t address_space_ldl_cached(MemoryRegionCache *cache, hwaddr addr,
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MemTxAttrs attrs, MemTxResult *result);
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uint64_t address_space_ldq_cached(MemoryRegionCache *cache, hwaddr addr,
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MemTxAttrs attrs, MemTxResult *result);
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void address_space_stl_notdirty_cached(MemoryRegionCache *cache, hwaddr addr,
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uint32_t val, MemTxAttrs attrs, MemTxResult *result);
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void address_space_stw_cached(MemoryRegionCache *cache, hwaddr addr, uint32_t val,
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MemTxAttrs attrs, MemTxResult *result);
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void address_space_stl_cached(MemoryRegionCache *cache, hwaddr addr, uint32_t val,
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MemTxAttrs attrs, MemTxResult *result);
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void address_space_stq_cached(MemoryRegionCache *cache, hwaddr addr, uint64_t val,
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MemTxAttrs attrs, MemTxResult *result);
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#endif
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/* page related stuff */
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@ -1419,6 +1419,125 @@ void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val);
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void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val);
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void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val);
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struct MemoryRegionCache {
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hwaddr xlat;
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void *ptr;
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hwaddr len;
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MemoryRegion *mr;
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bool is_write;
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};
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/* address_space_cache_init: prepare for repeated access to a physical
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* memory region
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*
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* @cache: #MemoryRegionCache to be filled
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* @as: #AddressSpace to be accessed
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* @addr: address within that address space
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* @len: length of buffer
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* @is_write: indicates the transfer direction
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*
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* Will only work with RAM, and may map a subset of the requested range by
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* returning a value that is less than @len. On failure, return a negative
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* errno value.
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*
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* Because it only works with RAM, this function can be used for
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* read-modify-write operations. In this case, is_write should be %true.
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*
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* Note that addresses passed to the address_space_*_cached functions
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* are relative to @addr.
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*/
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int64_t address_space_cache_init(MemoryRegionCache *cache,
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AddressSpace *as,
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hwaddr addr,
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hwaddr len,
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bool is_write);
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/**
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* address_space_cache_invalidate: complete a write to a #MemoryRegionCache
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*
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* @cache: The #MemoryRegionCache to operate on.
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* @addr: The first physical address that was written, relative to the
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* address that was passed to @address_space_cache_init.
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* @access_len: The number of bytes that were written starting at @addr.
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*/
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void address_space_cache_invalidate(MemoryRegionCache *cache,
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hwaddr addr,
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hwaddr access_len);
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/**
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* address_space_cache_destroy: free a #MemoryRegionCache
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*
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* @cache: The #MemoryRegionCache whose memory should be released.
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*/
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void address_space_cache_destroy(MemoryRegionCache *cache);
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/* address_space_ld*_cached: load from a cached #MemoryRegion
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* address_space_st*_cached: store into a cached #MemoryRegion
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*
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* These functions perform a load or store of the byte, word,
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* longword or quad to the specified address. The address is
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* a physical address in the AddressSpace, but it must lie within
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* a #MemoryRegion that was mapped with address_space_cache_init.
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*
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* The _le suffixed functions treat the data as little endian;
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* _be indicates big endian; no suffix indicates "same endianness
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* as guest CPU".
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*
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* The "guest CPU endianness" accessors are deprecated for use outside
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* target-* code; devices should be CPU-agnostic and use either the LE
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* or the BE accessors.
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*
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* @cache: previously initialized #MemoryRegionCache to be accessed
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* @addr: address within the address space
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* @val: data value, for stores
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* @attrs: memory transaction attributes
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* @result: location to write the success/failure of the transaction;
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* if NULL, this information is discarded
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*/
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uint32_t address_space_ldub_cached(MemoryRegionCache *cache, hwaddr addr,
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MemTxAttrs attrs, MemTxResult *result);
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uint32_t address_space_lduw_le_cached(MemoryRegionCache *cache, hwaddr addr,
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MemTxAttrs attrs, MemTxResult *result);
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uint32_t address_space_lduw_be_cached(MemoryRegionCache *cache, hwaddr addr,
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MemTxAttrs attrs, MemTxResult *result);
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uint32_t address_space_ldl_le_cached(MemoryRegionCache *cache, hwaddr addr,
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MemTxAttrs attrs, MemTxResult *result);
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uint32_t address_space_ldl_be_cached(MemoryRegionCache *cache, hwaddr addr,
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MemTxAttrs attrs, MemTxResult *result);
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uint64_t address_space_ldq_le_cached(MemoryRegionCache *cache, hwaddr addr,
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MemTxAttrs attrs, MemTxResult *result);
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uint64_t address_space_ldq_be_cached(MemoryRegionCache *cache, hwaddr addr,
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MemTxAttrs attrs, MemTxResult *result);
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void address_space_stb_cached(MemoryRegionCache *cache, hwaddr addr, uint32_t val,
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MemTxAttrs attrs, MemTxResult *result);
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void address_space_stw_le_cached(MemoryRegionCache *cache, hwaddr addr, uint32_t val,
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MemTxAttrs attrs, MemTxResult *result);
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void address_space_stw_be_cached(MemoryRegionCache *cache, hwaddr addr, uint32_t val,
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MemTxAttrs attrs, MemTxResult *result);
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void address_space_stl_le_cached(MemoryRegionCache *cache, hwaddr addr, uint32_t val,
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MemTxAttrs attrs, MemTxResult *result);
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void address_space_stl_be_cached(MemoryRegionCache *cache, hwaddr addr, uint32_t val,
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MemTxAttrs attrs, MemTxResult *result);
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void address_space_stq_le_cached(MemoryRegionCache *cache, hwaddr addr, uint64_t val,
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MemTxAttrs attrs, MemTxResult *result);
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void address_space_stq_be_cached(MemoryRegionCache *cache, hwaddr addr, uint64_t val,
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MemTxAttrs attrs, MemTxResult *result);
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uint32_t ldub_phys_cached(MemoryRegionCache *cache, hwaddr addr);
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uint32_t lduw_le_phys_cached(MemoryRegionCache *cache, hwaddr addr);
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uint32_t lduw_be_phys_cached(MemoryRegionCache *cache, hwaddr addr);
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uint32_t ldl_le_phys_cached(MemoryRegionCache *cache, hwaddr addr);
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uint32_t ldl_be_phys_cached(MemoryRegionCache *cache, hwaddr addr);
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uint64_t ldq_le_phys_cached(MemoryRegionCache *cache, hwaddr addr);
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uint64_t ldq_be_phys_cached(MemoryRegionCache *cache, hwaddr addr);
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void stb_phys_cached(MemoryRegionCache *cache, hwaddr addr, uint32_t val);
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void stw_le_phys_cached(MemoryRegionCache *cache, hwaddr addr, uint32_t val);
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void stw_be_phys_cached(MemoryRegionCache *cache, hwaddr addr, uint32_t val);
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void stl_le_phys_cached(MemoryRegionCache *cache, hwaddr addr, uint32_t val);
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void stl_be_phys_cached(MemoryRegionCache *cache, hwaddr addr, uint32_t val);
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void stq_le_phys_cached(MemoryRegionCache *cache, hwaddr addr, uint64_t val);
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void stq_be_phys_cached(MemoryRegionCache *cache, hwaddr addr, uint64_t val);
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/* address_space_translate: translate an address range into an address space
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* into a MemoryRegion and an address range into that section. Should be
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* called from an RCU critical section, to avoid that the last reference
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@ -1544,6 +1663,38 @@ MemTxResult address_space_read(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
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return result;
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}
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/**
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* address_space_read_cached: read from a cached RAM region
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*
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* @cache: Cached region to be addressed
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* @addr: address relative to the base of the RAM region
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* @buf: buffer with the data transferred
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* @len: length of the data transferred
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*/
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static inline void
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address_space_read_cached(MemoryRegionCache *cache, hwaddr addr,
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void *buf, int len)
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{
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assert(addr < cache->len && len <= cache->len - addr);
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memcpy(buf, cache->ptr + addr, len);
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}
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/**
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* address_space_write_cached: write to a cached RAM region
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*
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* @cache: Cached region to be addressed
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* @addr: address relative to the base of the RAM region
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* @buf: buffer with the data transferred
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* @len: length of the data transferred
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*/
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static inline void
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address_space_write_cached(MemoryRegionCache *cache, hwaddr addr,
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void *buf, int len)
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{
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assert(addr < cache->len && len <= cache->len - addr);
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memcpy(cache->ptr + addr, buf, len);
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}
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#endif
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#endif
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@ -45,6 +45,7 @@ typedef struct MachineState MachineState;
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typedef struct MemoryListener MemoryListener;
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typedef struct MemoryMappingList MemoryMappingList;
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typedef struct MemoryRegion MemoryRegion;
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typedef struct MemoryRegionCache MemoryRegionCache;
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typedef struct MemoryRegionSection MemoryRegionSection;
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typedef struct MigrationIncomingState MigrationIncomingState;
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typedef struct MigrationParams MigrationParams;
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