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target-tricore: add missing break in insn decode switch stmt 

After decoding/translating a RRR_DIVIDE/RRRR_EXTRACT_INSERT type instruction
we would simply fall through and would decode/translate another unintended
RRR2_MADD/RRRW_EXTRACT_INSERT instruction.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <1458547383-23102-2-git-send-email-kbastian@mail.uni-paderborn.de>
master
Bastian Koppelmann 2016-03-21 09:03:01 +01:00
parent 459621ac1a
commit 1f75cba8f8
1 changed files with 2 additions and 0 deletions
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2
target-tricore/translate.c
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@ -8632,6 +8632,7 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
break;
case OPCM_32_RRR_DIVIDE:
decode_rrr_divide(env, ctx);
break;
/* RRR2 Format */
case OPCM_32_RRR2_MADD:
decode_rrr2_madd(env, ctx);
@ -8661,6 +8662,7 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
/* RRRR format */
case OPCM_32_RRRR_EXTRACT_INSERT:
decode_rrrr_extract_insert(env, ctx);
break;
/* RRRW format */
case OPCM_32_RRRW_EXTRACT_INSERT:
decode_rrrw_extract_insert(env, ctx);