mirror of https://github.com/proxmox/mirror_qemu
target-arm: Convert performance monitor registers
Convert the v7 performance monitor cp15 registers to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>master
Peter Maydell
parent
4d31c59679
commit
200ac0ef87
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@ -132,10 +132,6 @@ static void arm_cpu_reset(CPUState *s)
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}
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env->vfp.xregs[ARM_VFP_FPEXC] = 0;
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env->cp15.c2_base_mask = 0xffffc000u;
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/* v7 performance monitor control register: same implementor
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* field as main ID register, and we implement no event counters.
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*/
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env->cp15.c9_pmcr = (cpu->midr & 0xff000000);
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#endif
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set_flush_to_zero(1, &env->vfp.standard_fp_status);
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set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
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@ -98,6 +98,97 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
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REGINFO_SENTINEL
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};
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static int pmreg_read(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t *value)
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{
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/* Generic performance monitor register read function for where
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* user access may be allowed by PMUSERENR.
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*/
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if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
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return EXCP_UDEF;
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}
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*value = CPREG_FIELD32(env, ri);
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return 0;
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}
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static int pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
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return EXCP_UDEF;
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}
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/* only the DP, X, D and E bits are writable */
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env->cp15.c9_pmcr &= ~0x39;
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env->cp15.c9_pmcr |= (value & 0x39);
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return 0;
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}
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static int pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
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return EXCP_UDEF;
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}
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value &= (1 << 31);
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env->cp15.c9_pmcnten |= value;
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return 0;
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}
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static int pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
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return EXCP_UDEF;
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}
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value &= (1 << 31);
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env->cp15.c9_pmcnten &= ~value;
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return 0;
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}
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static int pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
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return EXCP_UDEF;
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}
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env->cp15.c9_pmovsr &= ~value;
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return 0;
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}
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static int pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
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return EXCP_UDEF;
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}
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env->cp15.c9_pmxevtyper = value & 0xff;
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return 0;
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}
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static int pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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env->cp15.c9_pmuserenr = value & 1;
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return 0;
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}
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static int pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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/* We have no event counters so only the C bit can be changed */
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value &= (1 << 31);
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env->cp15.c9_pminten |= value;
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return 0;
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}
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static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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value &= (1 << 31);
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env->cp15.c9_pminten &= ~value;
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return 0;
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}
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static const ARMCPRegInfo v7_cp_reginfo[] = {
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/* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
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* debug components
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@ -109,6 +200,62 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
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/* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
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{ .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
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.access = PL1_W, .type = ARM_CP_NOP },
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/* Performance monitors are implementation defined in v7,
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* but with an ARM recommended set of registers, which we
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* follow (although we don't actually implement any counters)
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*
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* Performance registers fall into three categories:
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* (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
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* (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
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* (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
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* For the cases controlled by PMUSERENR we must set .access to PL0_RW
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* or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
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*/
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{ .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
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.access = PL0_RW, .resetvalue = 0,
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.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
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.readfn = pmreg_read, .writefn = pmcntenset_write },
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{ .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
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.access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
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.readfn = pmreg_read, .writefn = pmcntenclr_write },
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{ .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
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.access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
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.readfn = pmreg_read, .writefn = pmovsr_write },
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/* Unimplemented so WI. Strictly speaking write accesses in PL0 should
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* respect PMUSERENR.
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*/
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{ .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
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.access = PL0_W, .type = ARM_CP_NOP },
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/* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
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* We choose to RAZ/WI. XXX should respect PMUSERENR.
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*/
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{ .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
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.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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/* Unimplemented, RAZ/WI. XXX PMUSERENR */
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{ .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
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.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
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.access = PL0_RW,
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.fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
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.readfn = pmreg_read, .writefn = pmxevtyper_write },
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/* Unimplemented, RAZ/WI. XXX PMUSERENR */
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{ .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
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.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
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.access = PL0_R | PL1_RW,
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.fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
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.resetvalue = 0,
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.writefn = pmuserenr_write },
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{ .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
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.access = PL1_RW,
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.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
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.resetvalue = 0,
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.writefn = pmintenset_write },
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{ .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
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.access = PL1_RW,
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.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
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.resetvalue = 0,
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.writefn = pmintenclr_write },
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REGINFO_SENTINEL
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};
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@ -189,6 +336,16 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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define_arm_cp_regs(cpu, v6k_cp_reginfo);
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}
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if (arm_feature(env, ARM_FEATURE_V7)) {
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/* v7 performance monitor control register: same implementor
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* field as main ID register, and we implement no event counters.
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*/
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ARMCPRegInfo pmcr = {
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.name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
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.access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
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.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
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.readfn = pmreg_read, .writefn = pmcr_write
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};
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define_one_arm_cp_reg(cpu, &pmcr);
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define_arm_cp_regs(cpu, v7_cp_reginfo);
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} else {
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define_arm_cp_regs(cpu, not_v7_cp_reginfo);
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@ -1533,81 +1690,6 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
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case 1: /* TCM memory region registers. */
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/* Not implemented. */
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goto bad_reg;
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case 12: /* Performance monitor control */
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/* Performance monitors are implementation defined in v7,
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* but with an ARM recommended set of registers, which we
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* follow (although we don't actually implement any counters)
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*/
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if (!arm_feature(env, ARM_FEATURE_V7)) {
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goto bad_reg;
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}
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switch (op2) {
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case 0: /* performance monitor control register */
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/* only the DP, X, D and E bits are writable */
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env->cp15.c9_pmcr &= ~0x39;
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env->cp15.c9_pmcr |= (val & 0x39);
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break;
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case 1: /* Count enable set register */
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val &= (1 << 31);
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env->cp15.c9_pmcnten |= val;
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break;
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case 2: /* Count enable clear */
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val &= (1 << 31);
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env->cp15.c9_pmcnten &= ~val;
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break;
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case 3: /* Overflow flag status */
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env->cp15.c9_pmovsr &= ~val;
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break;
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case 4: /* Software increment */
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/* RAZ/WI since we don't implement the software-count event */
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break;
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case 5: /* Event counter selection register */
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/* Since we don't implement any events, writing to this register
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* is actually UNPREDICTABLE. So we choose to RAZ/WI.
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*/
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break;
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default:
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goto bad_reg;
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}
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break;
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case 13: /* Performance counters */
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if (!arm_feature(env, ARM_FEATURE_V7)) {
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goto bad_reg;
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}
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switch (op2) {
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case 0: /* Cycle count register: not implemented, so RAZ/WI */
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break;
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case 1: /* Event type select */
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env->cp15.c9_pmxevtyper = val & 0xff;
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break;
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case 2: /* Event count register */
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/* Unimplemented (we have no events), RAZ/WI */
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break;
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default:
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goto bad_reg;
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}
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break;
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case 14: /* Performance monitor control */
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if (!arm_feature(env, ARM_FEATURE_V7)) {
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goto bad_reg;
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}
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switch (op2) {
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case 0: /* user enable */
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env->cp15.c9_pmuserenr = val & 1;
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/* changes access rights for cp registers, so flush tbs */
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tb_flush(env);
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break;
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case 1: /* interrupt enable set */
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/* We have no event counters so only the C bit can be changed */
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val &= (1 << 31);
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env->cp15.c9_pminten |= val;
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break;
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case 2: /* interrupt enable clear */
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val &= (1 << 31);
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env->cp15.c9_pminten &= ~val;
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break;
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}
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break;
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default:
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goto bad_reg;
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}
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@ -1964,51 +2046,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
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goto bad_reg;
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}
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break;
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case 12: /* Performance monitor control */
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if (!arm_feature(env, ARM_FEATURE_V7)) {
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goto bad_reg;
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}
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switch (op2) {
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case 0: /* performance monitor control register */
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return env->cp15.c9_pmcr;
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case 1: /* count enable set */
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case 2: /* count enable clear */
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return env->cp15.c9_pmcnten;
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case 3: /* overflow flag status */
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return env->cp15.c9_pmovsr;
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case 4: /* software increment */
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case 5: /* event counter selection register */
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return 0; /* Unimplemented, RAZ/WI */
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default:
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goto bad_reg;
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}
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case 13: /* Performance counters */
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if (!arm_feature(env, ARM_FEATURE_V7)) {
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goto bad_reg;
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}
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switch (op2) {
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case 1: /* Event type select */
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return env->cp15.c9_pmxevtyper;
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case 0: /* Cycle count register */
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case 2: /* Event count register */
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/* Unimplemented, so RAZ/WI */
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return 0;
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default:
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goto bad_reg;
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}
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case 14: /* Performance monitor control */
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if (!arm_feature(env, ARM_FEATURE_V7)) {
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goto bad_reg;
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}
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switch (op2) {
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case 0: /* user enable */
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return env->cp15.c9_pmuserenr;
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case 1: /* interrupt enable set */
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case 2: /* interrupt enable clear */
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return env->cp15.c9_pminten;
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default:
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goto bad_reg;
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}
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default:
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goto bad_reg;
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}
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@ -2439,30 +2439,6 @@ static int disas_dsp_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
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return 1;
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}
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static int cp15_user_ok(CPUARMState *env, uint32_t insn)
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{
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int cpn = (insn >> 16) & 0xf;
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int cpm = insn & 0xf;
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int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
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if (arm_feature(env, ARM_FEATURE_V7) && cpn == 9) {
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/* Performance monitor registers fall into three categories:
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* (a) always UNDEF in usermode
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* (b) UNDEF only if PMUSERENR.EN is 0
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* (c) always read OK and UNDEF on write (PMUSERENR only)
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*/
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if ((cpm == 12 && (op < 6)) ||
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(cpm == 13 && (op < 3))) {
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return env->cp15.c9_pmuserenr;
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} else if (cpm == 14 && op == 0 && (insn & ARM_CP_RW_BIT)) {
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/* PMUSERENR, read only */
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return 1;
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}
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return 0;
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}
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return 0;
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}
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/* Disassemble system coprocessor (cp15) instruction. Return nonzero if
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instruction is not defined. */
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static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
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@ -2487,7 +2463,7 @@ static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
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return 1;
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}
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if (IS_USER(s) && !cp15_user_ok(env, insn)) {
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if (IS_USER(s)) {
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return 1;
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}
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