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ppc/pnv: turn PnvPHB4 into a PnvPHB backend 

Change the parent type of the PnvPHB4 device to TYPE_PARENT since the
PCI bus is going to be initialized by the PnvPHB parent. Functions that
needs to access the bus via a PnvPHB4 object can do so via the
phb4->phb_base pointer.

pnv_phb4_pec now creates a PnvPHB object.

The powernv9 machine class will create PnvPHB devices with version '4'.
powernv10 will create using version '5'. Both are using global machine
properties in their class_init() to do that.

These changes will benefit us when adding PnvPHB user creatable devices
for powernv9 and powernv10.

Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220624084921.399219-6-danielhb413@gmail.com>
master
Daniel Henrique Barboza 2022-06-24 05:49:14 -03:00
parent fe5bfd4bb8
commit 210aacb3b9
4 changed files with 27 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
hw/pci-host/pnv_phb4.c
View File

@ -33,7 +33,7 @@
static PCIDevice *pnv_phb4_find_cfg_dev(PnvPHB4 *phb)
{
PCIHostState *pci = PCI_HOST_BRIDGE(phb);
PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base);
uint64_t addr = phb->regs[PHB_CONFIG_ADDRESS >> 3];
uint8_t bus, devfn;
@ -129,7 +129,7 @@ static uint64_t pnv_phb4_config_read(PnvPHB4 *phb, unsigned off,
static void pnv_phb4_rc_config_write(PnvPHB4 *phb, unsigned off,
unsigned size, uint64_t val)
{
PCIHostState *pci = PCI_HOST_BRIDGE(phb);
PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base);
PCIDevice *pdev;
if (size != 4) {
@ -150,7 +150,7 @@ static void pnv_phb4_rc_config_write(PnvPHB4 *phb, unsigned off,
static uint64_t pnv_phb4_rc_config_read(PnvPHB4 *phb, unsigned off,
unsigned size)
{
PCIHostState *pci = PCI_HOST_BRIDGE(phb);
PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base);
PCIDevice *pdev;
uint64_t val;
@ -1558,8 +1558,6 @@ void pnv_phb4_bus_init(DeviceState *dev, PnvPHB4 *phb)
static void pnv_phb4_realize(DeviceState *dev, Error **errp)
{
PnvPHB4 *phb = PNV_PHB4(dev);
PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(phb->pec);
PCIHostState *pci = PCI_HOST_BRIDGE(dev);
XiveSource *xsrc = &phb->xsrc;
int nr_irqs;
char name[32];
@ -1573,12 +1571,6 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp)
memory_region_init_io(&phb->mr_regs, OBJECT(phb), &pnv_phb4_reg_ops, phb,
name, 0x2000);
pnv_phb4_bus_init(dev, phb);
/* Add a single Root port if running with defaults */
pnv_phb_attach_root_port(pci, pecc->rp_model,
phb->phb_id, phb->chip_id);
/* Setup XIVE Source */
if (phb->big_phb) {
nr_irqs = PNV_PHB4_MAX_INTs;
@ -1598,16 +1590,6 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp)
pnv_phb4_xscom_realize(phb);
}
static const char *pnv_phb4_root_bus_path(PCIHostState *host_bridge,
PCIBus *rootbus)
{
PnvPHB4 *phb = PNV_PHB4(host_bridge);
snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x",
phb->chip_id, phb->phb_id);
return phb->bus_path;
}
/*
* Address base trigger mode (POWER10)
*
@ -1692,19 +1674,17 @@ static Property pnv_phb4_properties[] = {
DEFINE_PROP_UINT32("chip-id", PnvPHB4, chip_id, 0),
DEFINE_PROP_LINK("pec", PnvPHB4, pec, TYPE_PNV_PHB4_PEC,
PnvPhb4PecState *),
DEFINE_PROP_LINK("phb-base", PnvPHB4, phb_base, TYPE_PNV_PHB, PnvPHB *),
DEFINE_PROP_END_OF_LIST(),
};
static void pnv_phb4_class_init(ObjectClass *klass, void *data)
{
PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass);
hc->root_bus_path = pnv_phb4_root_bus_path;
dc->realize = pnv_phb4_realize;
device_class_set_props(dc, pnv_phb4_properties);
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->user_creatable = false;
xfc->notify = pnv_phb4_xive_notify;
@ -1712,7 +1692,7 @@ static void pnv_phb4_class_init(ObjectClass *klass, void *data)
static const TypeInfo pnv_phb4_type_info = {
.name = TYPE_PNV_PHB4,
.parent = TYPE_PCIE_HOST_BRIDGE,
.parent = TYPE_DEVICE,
.instance_init = pnv_phb4_instance_init,
.instance_size = sizeof(PnvPHB4),
.class_init = pnv_phb4_class_init,

3
hw/pci-host/pnv_phb4_pec.c
View File

@ -115,8 +115,7 @@ static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec,
int stack_no,
Error **errp)
{
PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
PnvPHB4 *phb = PNV_PHB4(qdev_new(pecc->phb_type));
PnvPHB *phb = PNV_PHB(qdev_new(TYPE_PNV_PHB));
int phb_id = pnv_phb4_pec_get_phb_id(pec, stack_no);
object_property_add_child(OBJECT(pec), "phb[*]", OBJECT(phb));

20
hw/ppc/pnv.c
View File

@ -672,11 +672,14 @@ static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque)
{
Monitor *mon = opaque;
PnvPHB4 *phb4 = (PnvPHB4 *) object_dynamic_cast(child, TYPE_PNV_PHB4);
PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB);
if (phb4) {
pnv_phb4_pic_print_info(phb4, mon);
if (!phb) {
return 0;
}
pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), mon);
return 0;
}
@ -2147,8 +2150,14 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
static const char compat[] = "qemu,powernv9\0ibm,powernv";
static GlobalProperty phb_compat[] = {
{ TYPE_PNV_PHB, "version", "4" },
};
mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
xfc->match_nvt = pnv_match_nvt;
mc->alias = "powernv";
@ -2165,8 +2174,13 @@ static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
static const char compat[] = "qemu,powernv10\0ibm,powernv";
static GlobalProperty phb_compat[] = {
{ TYPE_PNV_PHB, "version", "5" },
};
mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
pmc->compat = compat;
pmc->compat_size = sizeof(compat);

5
include/hw/pci-host/pnv_phb4.h
View File

@ -18,6 +18,7 @@
typedef struct PnvPhb4PecState PnvPhb4PecState;
typedef struct PnvPhb4PecStack PnvPhb4PecStack;
typedef struct PnvPHB4 PnvPHB4;
typedef struct PnvPHB PnvPHB;
typedef struct PnvChip PnvChip;
/*
@ -78,7 +79,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4, PNV_PHB4)
#define PCI_MMIO_TOTAL_SIZE (0x1ull << 60)
struct PnvPHB4 {
PCIExpressHost parent_obj;
DeviceState parent;
PnvPHB *phb_base;
uint32_t chip_id;
uint32_t phb_id;