mirror of https://github.com/proxmox/mirror_qemu
hw/riscv/sifive_u: Create a SiFive U SoC object
Create a SiFive Unleashed U54 SoC and use that in the sifive_u machine. We leave the SoC, RAM, device tree and reset/fdt loading as part of the machine. All the other device creation has been moved to the SoC. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Michael Clark <mjc@sifive.com>master
parent
cee35138b5
commit
2308092b2b
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@ -116,10 +116,10 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
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for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
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for (cpu = s->soc.cpus.num_harts - 1; cpu >= 0; cpu--) {
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nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
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char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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char *isa = riscv_isa_string(&s->soc.harts[cpu]);
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char *isa = riscv_isa_string(&s->soc.cpus.harts[cpu]);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
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SIFIVE_U_CLOCK_FREQ);
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@ -140,8 +140,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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g_free(nodename);
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}
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cells = g_new0(uint32_t, s->soc.num_harts * 4);
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for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
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cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4);
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for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) {
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nodename =
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g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
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@ -159,12 +159,12 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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0x0, memmap[SIFIVE_U_CLINT].base,
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0x0, memmap[SIFIVE_U_CLINT].size);
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qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
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cells, s->soc.num_harts * sizeof(uint32_t) * 4);
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cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4);
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g_free(cells);
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g_free(nodename);
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cells = g_new0(uint32_t, s->soc.num_harts * 4);
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for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
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cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4);
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for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) {
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nodename =
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g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
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@ -181,7 +181,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
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qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
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cells, s->soc.num_harts * sizeof(uint32_t) * 4);
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cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4);
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[SIFIVE_U_PLIC].base,
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0x0, memmap[SIFIVE_U_PLIC].size);
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@ -217,17 +217,12 @@ static void riscv_sifive_u_init(MachineState *machine)
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SiFiveUState *s = g_new0(SiFiveUState, 1);
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MemoryRegion *system_memory = get_system_memory();
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MemoryRegion *main_mem = g_new(MemoryRegion, 1);
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MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
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int i;
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/* Initialize SOC */
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object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY);
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/* Initialize SoC */
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object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_U_SOC);
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object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
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&error_abort);
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object_property_set_str(OBJECT(&s->soc), SIFIVE_U_CPU, "cpu-type",
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&error_abort);
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object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
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&error_abort);
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object_property_set_bool(OBJECT(&s->soc), true, "realized",
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&error_abort);
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@ -235,17 +230,11 @@ static void riscv_sifive_u_init(MachineState *machine)
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memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
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machine->ram_size, &error_fatal);
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memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
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main_mem);
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main_mem);
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/* create device tree */
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create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
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/* boot rom */
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memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom",
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memmap[SIFIVE_U_MROM].size, &error_fatal);
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memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
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mask_rom);
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if (machine->kernel_filename) {
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load_kernel(machine->kernel_filename);
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}
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@ -284,6 +273,36 @@ static void riscv_sifive_u_init(MachineState *machine)
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rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
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memmap[SIFIVE_U_MROM].base + sizeof(reset_vec),
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&address_space_memory);
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}
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static void riscv_sifive_u_soc_init(Object *obj)
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{
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SiFiveUSoCState *s = RISCV_U_SOC(obj);
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object_initialize(&s->cpus, sizeof(s->cpus), TYPE_RISCV_HART_ARRAY);
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object_property_add_child(obj, "cpus", OBJECT(&s->cpus),
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&error_abort);
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object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type",
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&error_abort);
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object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts",
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&error_abort);
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}
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static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
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{
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SiFiveUSoCState *s = RISCV_U_SOC(dev);
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const struct MemmapEntry *memmap = sifive_u_memmap;
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MemoryRegion *system_memory = get_system_memory();
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MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
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object_property_set_bool(OBJECT(&s->cpus), true, "realized",
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&error_abort);
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/* boot rom */
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memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom",
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memmap[SIFIVE_U_MROM].size, &error_fatal);
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memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
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mask_rom);
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/* MMIO */
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s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
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@ -314,3 +333,27 @@ static void riscv_sifive_u_machine_init(MachineClass *mc)
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}
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DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
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static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = riscv_sifive_u_soc_realize;
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/* Reason: Uses serial_hds in realize function, thus can't be used twice */
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dc->user_creatable = false;
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}
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static const TypeInfo riscv_sifive_u_soc_type_info = {
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.name = TYPE_RISCV_U_SOC,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(SiFiveUSoCState),
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.instance_init = riscv_sifive_u_soc_init,
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.class_init = riscv_sifive_u_soc_class_init,
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};
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static void riscv_sifive_u_soc_register_types(void)
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{
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type_register_static(&riscv_sifive_u_soc_type_info);
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}
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type_init(riscv_sifive_u_soc_register_types)
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@ -19,13 +19,25 @@
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#ifndef HW_SIFIVE_U_H
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#define HW_SIFIVE_U_H
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#define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
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#define RISCV_U_SOC(obj) \
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OBJECT_CHECK(SiFiveUSoCState, (obj), TYPE_RISCV_U_SOC)
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typedef struct SiFiveUSoCState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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RISCVHartArrayState cpus;
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DeviceState *plic;
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} SiFiveUSoCState;
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typedef struct SiFiveUState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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RISCVHartArrayState soc;
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DeviceState *plic;
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SiFiveUSoCState soc;
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void *fdt;
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int fdt_size;
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} SiFiveUState;
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