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ppc: convert to memory API 

Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
master
Avi Kivity 2011-08-08 16:09:17 +03:00 committed by Anthony Liguori
parent b0ce84e50b
commit 23c5e4cab2
15 changed files with 203 additions and 219 deletions
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6
hw/cuda.c
View File

@ -117,6 +117,7 @@ typedef struct CUDATimer {
} CUDATimer; } CUDATimer;
typedef struct CUDAState { typedef struct CUDAState {
MemoryRegion mem;
/* cuda registers */ /* cuda registers */
uint8_t b; /* B-side data */ uint8_t b; /* B-side data */
uint8_t a; /* A-side data */ uint8_t a; /* A-side data */
@ -722,7 +723,7 @@ static void cuda_reset(void *opaque)
set_counter(s, &s->timers[1], 0xffff); set_counter(s, &s->timers[1], 0xffff);
} }
void cuda_init (int *cuda_mem_index, qemu_irq irq) void cuda_init (MemoryRegion **cuda_mem, qemu_irq irq)
{ {
struct tm tm; struct tm tm;
CUDAState *s = &cuda_state; CUDAState *s = &cuda_state;
@ -738,8 +739,9 @@ void cuda_init (int *cuda_mem_index, qemu_irq irq)
s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET; s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET;
s->adb_poll_timer = qemu_new_timer_ns(vm_clock, cuda_adb_poll, s); s->adb_poll_timer = qemu_new_timer_ns(vm_clock, cuda_adb_poll, s);
*cuda_mem_index = cpu_register_io_memory(cuda_read, cuda_write, s, cpu_register_io_memory(cuda_read, cuda_write, s,
DEVICE_NATIVE_ENDIAN); DEVICE_NATIVE_ENDIAN);
*cuda_mem = &s->mem;
vmstate_register(NULL, -1, &vmstate_cuda, s); vmstate_register(NULL, -1, &vmstate_cuda, s);
qemu_register_reset(cuda_reset, s); qemu_register_reset(cuda_reset, s);
} }

42
hw/escc.c
View File

@ -126,7 +126,7 @@ struct SerialState {
SysBusDevice busdev; SysBusDevice busdev;
struct ChannelState chn[2]; struct ChannelState chn[2];
uint32_t it_shift; uint32_t it_shift;
int mmio_index; MemoryRegion mmio;
uint32_t disabled; uint32_t disabled;
uint32_t frequency; uint32_t frequency;
}; };
@ -490,7 +490,8 @@ static void escc_update_parameters(ChannelState *s)
qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
} }
static void escc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) static void escc_mem_write(void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned size)
{ {
SerialState *serial = opaque; SerialState *serial = opaque;
ChannelState *s; ChannelState *s;
@ -592,7 +593,8 @@ static void escc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
} }
} }
static uint32_t escc_mem_readb(void *opaque, target_phys_addr_t addr) static uint64_t escc_mem_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{ {
SerialState *serial = opaque; SerialState *serial = opaque;
ChannelState *s; ChannelState *s;
@ -627,6 +629,16 @@ static uint32_t escc_mem_readb(void *opaque, target_phys_addr_t addr)
return 0; return 0;
} }
static const MemoryRegionOps escc_mem_ops = {
.read = escc_mem_read,
.write = escc_mem_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 1,
.max_access_size = 1,
},
};
static int serial_can_receive(void *opaque) static int serial_can_receive(void *opaque)
{ {
ChannelState *s = opaque; ChannelState *s = opaque;
@ -668,18 +680,6 @@ static void serial_event(void *opaque, int event)
serial_receive_break(s); serial_receive_break(s);
} }
static CPUReadMemoryFunc * const escc_mem_read[3] = {
escc_mem_readb,
NULL,
NULL,
};
static CPUWriteMemoryFunc * const escc_mem_write[3] = {
escc_mem_writeb,
NULL,
NULL,
};
static const VMStateDescription vmstate_escc_chn = { static const VMStateDescription vmstate_escc_chn = {
.name ="escc_chn", .name ="escc_chn",
.version_id = 2, .version_id = 2,
@ -712,7 +712,7 @@ static const VMStateDescription vmstate_escc = {
} }
}; };
int escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB, MemoryRegion *escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
CharDriverState *chrA, CharDriverState *chrB, CharDriverState *chrA, CharDriverState *chrB,
int clock, int it_shift) int clock, int it_shift)
{ {
@ -737,7 +737,7 @@ int escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
} }
d = FROM_SYSBUS(SerialState, s); d = FROM_SYSBUS(SerialState, s);
return d->mmio_index; return &d->mmio;
} }
static const uint8_t keycodes[128] = { static const uint8_t keycodes[128] = {
@ -901,7 +901,6 @@ void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
static int escc_init1(SysBusDevice *dev) static int escc_init1(SysBusDevice *dev)
{ {
SerialState *s = FROM_SYSBUS(SerialState, dev); SerialState *s = FROM_SYSBUS(SerialState, dev);
int io;
unsigned int i; unsigned int i;
s->chn[0].disabled = s->disabled; s->chn[0].disabled = s->disabled;
@ -918,10 +917,9 @@ static int escc_init1(SysBusDevice *dev)
s->chn[0].otherchn = &s->chn[1]; s->chn[0].otherchn = &s->chn[1];
s->chn[1].otherchn = &s->chn[0]; s->chn[1].otherchn = &s->chn[0];
io = cpu_register_io_memory(escc_mem_read, escc_mem_write, s, memory_region_init_io(&s->mmio, &escc_mem_ops, s, "escc",
DEVICE_NATIVE_ENDIAN); ESCC_SIZE << s->it_shift);
sysbus_init_mmio(dev, ESCC_SIZE << s->it_shift, io); sysbus_init_mmio_region(dev, &s->mmio);
s->mmio_index = io;
if (s->chn[0].type == mouse) { if (s->chn[0].type == mouse) {
qemu_add_mouse_event_handler(sunmouse_event, &s->chn[0], 0, qemu_add_mouse_event_handler(sunmouse_event, &s->chn[0], 0,

2
hw/escc.h
View File

@ -1,6 +1,6 @@
/* escc.c */ /* escc.c */
#define ESCC_SIZE 4 #define ESCC_SIZE 4
int escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB, MemoryRegion *escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
CharDriverState *chrA, CharDriverState *chrB, CharDriverState *chrA, CharDriverState *chrB,
int clock, int it_shift); int clock, int it_shift);

29
hw/heathrow_pic.c
View File

@ -43,6 +43,7 @@ typedef struct HeathrowPIC {
} HeathrowPIC; } HeathrowPIC;
typedef struct HeathrowPICS { typedef struct HeathrowPICS {
MemoryRegion mem;
HeathrowPIC pics[2]; HeathrowPIC pics[2];
qemu_irq *irqs; qemu_irq *irqs;
} HeathrowPICS; } HeathrowPICS;
@ -62,7 +63,8 @@ static void heathrow_pic_update(HeathrowPICS *s)
} }
} }
static void pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value) static void pic_write(void *opaque, target_phys_addr_t addr,
uint64_t value, unsigned size)
{ {
HeathrowPICS *s = opaque; HeathrowPICS *s = opaque;
HeathrowPIC *pic; HeathrowPIC *pic;
@ -89,7 +91,8 @@ static void pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
} }
} }
static uint32_t pic_readl (void *opaque, target_phys_addr_t addr) static uint64_t pic_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{ {
HeathrowPICS *s = opaque; HeathrowPICS *s = opaque;
HeathrowPIC *pic; HeathrowPIC *pic;
@ -120,19 +123,12 @@ static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)
return value; return value;
} }
static CPUWriteMemoryFunc * const pic_write[] = { static const MemoryRegionOps heathrow_pic_ops = {
&pic_writel, .read = pic_read,
&pic_writel, .write = pic_write,
&pic_writel, .endianness = DEVICE_NATIVE_ENDIAN,
}; };
static CPUReadMemoryFunc * const pic_read[] = {
&pic_readl,
&pic_readl,
&pic_readl,
};
static void heathrow_pic_set_irq(void *opaque, int num, int level) static void heathrow_pic_set_irq(void *opaque, int num, int level)
{ {
HeathrowPICS *s = opaque; HeathrowPICS *s = opaque;
@ -201,7 +197,7 @@ static void heathrow_pic_reset(void *opaque)
s->pics[1].level_triggered = 0x1ff00000; s->pics[1].level_triggered = 0x1ff00000;
} }
qemu_irq *heathrow_pic_init(int *pmem_index, qemu_irq *heathrow_pic_init(MemoryRegion **pmem,
int nb_cpus, qemu_irq **irqs) int nb_cpus, qemu_irq **irqs)
{ {
HeathrowPICS *s; HeathrowPICS *s;
@ -209,8 +205,9 @@ qemu_irq *heathrow_pic_init(int *pmem_index,
s = qemu_mallocz(sizeof(HeathrowPICS)); s = qemu_mallocz(sizeof(HeathrowPICS));
/* only 1 CPU */ /* only 1 CPU */
s->irqs = irqs[0]; s->irqs = irqs[0];
*pmem_index = cpu_register_io_memory(pic_read, pic_write, s, memory_region_init_io(&s->mem, &heathrow_pic_ops, s,
DEVICE_LITTLE_ENDIAN); "heathrow-pic", 0x1000);
*pmem = &s->mem;
vmstate_register(NULL, -1, &vmstate_heathrow_pic, s); vmstate_register(NULL, -1, &vmstate_heathrow_pic, s);
qemu_register_reset(heathrow_pic_reset, s); qemu_register_reset(heathrow_pic_reset, s);

2
hw/ide.h
View File

@ -19,7 +19,7 @@ PCIDevice *pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn);
void vt82c686b_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn); void vt82c686b_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn);
/* ide-macio.c */ /* ide-macio.c */
int pmac_ide_init (DriveInfo **hd_table, qemu_irq irq, MemoryRegion *pmac_ide_init (DriveInfo **hd_table, qemu_irq irq,
void *dbdma, int channel, qemu_irq dma_irq); void *dbdma, int channel, qemu_irq dma_irq);
/* ide-mmio.c */ /* ide-mmio.c */

36
hw/ide/macio.c
View File

@ -35,6 +35,7 @@
/* MacIO based PowerPC IDE */ /* MacIO based PowerPC IDE */
typedef struct MACIOIDEState { typedef struct MACIOIDEState {
MemoryRegion mem;
IDEBus bus; IDEBus bus;
BlockDriverAIOCB *aiocb; BlockDriverAIOCB *aiocb;
} MACIOIDEState; } MACIOIDEState;
@ -281,16 +282,20 @@ static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
return retval; return retval;
} }
static CPUWriteMemoryFunc * const pmac_ide_write[] = { static MemoryRegionOps pmac_ide_ops = {
pmac_ide_writeb, .old_mmio = {
pmac_ide_writew, .write = {
pmac_ide_writel, pmac_ide_writeb,
}; pmac_ide_writew,
pmac_ide_writel,
static CPUReadMemoryFunc * const pmac_ide_read[] = { },
pmac_ide_readb, .read = {
pmac_ide_readw, pmac_ide_readb,
pmac_ide_readl, pmac_ide_readw,
pmac_ide_readl,
},
},
.endianness = DEVICE_NATIVE_ENDIAN,
}; };
static const VMStateDescription vmstate_pmac = { static const VMStateDescription vmstate_pmac = {
@ -315,11 +320,10 @@ static void pmac_ide_reset(void *opaque)
/* hd_table must contain 4 block drivers */ /* hd_table must contain 4 block drivers */
/* PowerMac uses memory mapped registers, not I/O. Return the memory /* PowerMac uses memory mapped registers, not I/O. Return the memory
I/O index to access the ide. */ I/O index to access the ide. */
int pmac_ide_init (DriveInfo **hd_table, qemu_irq irq, MemoryRegion *pmac_ide_init (DriveInfo **hd_table, qemu_irq irq,
void *dbdma, int channel, qemu_irq dma_irq) void *dbdma, int channel, qemu_irq dma_irq)
{ {
MACIOIDEState *d; MACIOIDEState *d;
int pmac_ide_memory;
d = qemu_mallocz(sizeof(MACIOIDEState)); d = qemu_mallocz(sizeof(MACIOIDEState));
ide_init2_with_non_qdev_drives(&d->bus, hd_table[0], hd_table[1], irq); ide_init2_with_non_qdev_drives(&d->bus, hd_table[0], hd_table[1], irq);
@ -327,11 +331,9 @@ int pmac_ide_init (DriveInfo **hd_table, qemu_irq irq,
if (dbdma) if (dbdma)
DBDMA_register_channel(dbdma, channel, dma_irq, pmac_ide_transfer, pmac_ide_flush, d); DBDMA_register_channel(dbdma, channel, dma_irq, pmac_ide_transfer, pmac_ide_flush, d);
pmac_ide_memory = cpu_register_io_memory(pmac_ide_read, memory_region_init_io(&d->mem, &pmac_ide_ops, d, "pmac-ide", 0x1000);
pmac_ide_write, d,
DEVICE_NATIVE_ENDIAN);
vmstate_register(NULL, 0, &vmstate_pmac, d); vmstate_register(NULL, 0, &vmstate_pmac, d);
qemu_register_reset(pmac_ide_reset, d); qemu_register_reset(pmac_ide_reset, d);
return pmac_ide_memory; return &d->mem;
} }

32
hw/mac_dbdma.c
View File

@ -166,6 +166,7 @@ typedef struct DBDMA_channel {
} DBDMA_channel; } DBDMA_channel;
typedef struct { typedef struct {
MemoryRegion mem;
DBDMA_channel channels[DBDMA_CHANNELS]; DBDMA_channel channels[DBDMA_CHANNELS];
} DBDMAState; } DBDMAState;
@ -703,8 +704,8 @@ dbdma_control_write(DBDMA_channel *ch)
ch->flush(&ch->io); ch->flush(&ch->io);
} }
static void dbdma_writel (void *opaque, static void dbdma_write(void *opaque, target_phys_addr_t addr,
target_phys_addr_t addr, uint32_t value) uint64_t value, unsigned size)
{ {
int channel = addr >> DBDMA_CHANNEL_SHIFT; int channel = addr >> DBDMA_CHANNEL_SHIFT;
DBDMAState *s = opaque; DBDMAState *s = opaque;
@ -753,7 +754,8 @@ static void dbdma_writel (void *opaque,
} }
} }
static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr) static uint64_t dbdma_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{ {
uint32_t value; uint32_t value;
int channel = addr >> DBDMA_CHANNEL_SHIFT; int channel = addr >> DBDMA_CHANNEL_SHIFT;
@ -798,16 +800,14 @@ static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr)
return value; return value;
} }
static CPUWriteMemoryFunc * const dbdma_write[] = { static const MemoryRegionOps dbdma_ops = {
NULL, .read = dbdma_read,
NULL, .write = dbdma_write,
dbdma_writel, .endianness = DEVICE_LITTLE_ENDIAN,
}; .valid = {
.min_access_size = 4,
static CPUReadMemoryFunc * const dbdma_read[] = { .max_access_size = 4,
NULL, },
NULL,
dbdma_readl,
}; };
static const VMStateDescription vmstate_dbdma_channel = { static const VMStateDescription vmstate_dbdma_channel = {
@ -842,14 +842,14 @@ static void dbdma_reset(void *opaque)
memset(s->channels[i].regs, 0, DBDMA_SIZE); memset(s->channels[i].regs, 0, DBDMA_SIZE);
} }
void* DBDMA_init (int *dbdma_mem_index) void* DBDMA_init (MemoryRegion **dbdma_mem)
{ {
DBDMAState *s; DBDMAState *s;
s = qemu_mallocz(sizeof(DBDMAState)); s = qemu_mallocz(sizeof(DBDMAState));
*dbdma_mem_index = cpu_register_io_memory(dbdma_read, dbdma_write, s, memory_region_init_io(&s->mem, &dbdma_ops, s, "dbdma", 0x1000);
DEVICE_LITTLE_ENDIAN); *dbdma_mem = &s->mem;
vmstate_register(NULL, -1, &vmstate_dbdma, s); vmstate_register(NULL, -1, &vmstate_dbdma, s);
qemu_register_reset(dbdma_reset, s); qemu_register_reset(dbdma_reset, s);

4
hw/mac_dbdma.h
View File

@ -20,6 +20,8 @@
* THE SOFTWARE. * THE SOFTWARE.
*/ */
#include "memory.h"
typedef struct DBDMA_io DBDMA_io; typedef struct DBDMA_io DBDMA_io;
typedef void (*DBDMA_flush)(DBDMA_io *io); typedef void (*DBDMA_flush)(DBDMA_io *io);
@ -40,4 +42,4 @@ void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq,
DBDMA_rw rw, DBDMA_flush flush, DBDMA_rw rw, DBDMA_flush flush,
void *opaque); void *opaque);
void DBDMA_schedule(void); void DBDMA_schedule(void);
void* DBDMA_init (int *dbdma_mem_index); void* DBDMA_init (MemoryRegion **dbdma_mem);

39
hw/mac_nvram.c
View File

@ -39,7 +39,7 @@
struct MacIONVRAMState { struct MacIONVRAMState {
uint32_t size; uint32_t size;
int mem_index; MemoryRegion mem;
unsigned int it_shift; unsigned int it_shift;
uint8_t *data; uint8_t *data;
}; };
@ -71,8 +71,8 @@ void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val)
} }
/* macio style NVRAM device */ /* macio style NVRAM device */
static void macio_nvram_writeb (void *opaque, static void macio_nvram_writeb(void *opaque, target_phys_addr_t addr,
target_phys_addr_t addr, uint32_t value) uint64_t value, unsigned size)
{ {
MacIONVRAMState *s = opaque; MacIONVRAMState *s = opaque;
@ -81,7 +81,8 @@ static void macio_nvram_writeb (void *opaque,
NVR_DPRINTF("writeb addr %04x val %x\n", (int)addr, value); NVR_DPRINTF("writeb addr %04x val %x\n", (int)addr, value);
} }
static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr) static uint64_t macio_nvram_readb(void *opaque, target_phys_addr_t addr,
unsigned size)
{ {
MacIONVRAMState *s = opaque; MacIONVRAMState *s = opaque;
uint32_t value; uint32_t value;
@ -93,16 +94,10 @@ static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr)
return value; return value;
} }
static CPUWriteMemoryFunc * const nvram_write[] = { static const MemoryRegionOps macio_nvram_ops = {
&macio_nvram_writeb, .read = macio_nvram_readb,
&macio_nvram_writeb, .write = macio_nvram_writeb,
&macio_nvram_writeb, .endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUReadMemoryFunc * const nvram_read[] = {
&macio_nvram_readb,
&macio_nvram_readb,
&macio_nvram_readb,
}; };
static const VMStateDescription vmstate_macio_nvram = { static const VMStateDescription vmstate_macio_nvram = {
@ -121,7 +116,7 @@ static void macio_nvram_reset(void *opaque)
{ {
} }
MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size, MacIONVRAMState *macio_nvram_init (target_phys_addr_t size,
unsigned int it_shift) unsigned int it_shift)
{ {
MacIONVRAMState *s; MacIONVRAMState *s;
@ -131,22 +126,18 @@ MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size,
s->size = size; s->size = size;
s->it_shift = it_shift; s->it_shift = it_shift;
s->mem_index = cpu_register_io_memory(nvram_read, nvram_write, s, memory_region_init_io(&s->mem, &macio_nvram_ops, s, "macio-nvram",
DEVICE_NATIVE_ENDIAN); size << it_shift);
*mem_index = s->mem_index;
vmstate_register(NULL, -1, &vmstate_macio_nvram, s); vmstate_register(NULL, -1, &vmstate_macio_nvram, s);
qemu_register_reset(macio_nvram_reset, s); qemu_register_reset(macio_nvram_reset, s);
return s; return s;
} }
void macio_nvram_map (void *opaque, target_phys_addr_t mem_base) void macio_nvram_setup_bar(MacIONVRAMState *s, MemoryRegion *bar,
target_phys_addr_t mem_base)
{ {
MacIONVRAMState *s; memory_region_add_subregion(bar, mem_base, &s->mem);
s = opaque;
cpu_register_physical_memory(mem_base, s->size << s->it_shift,
s->mem_index);
} }
/* Set up a system OpenBIOS NVRAM partition */ /* Set up a system OpenBIOS NVRAM partition */

74
hw/macio.c
View File

@ -30,58 +30,55 @@
typedef struct macio_state_t macio_state_t; typedef struct macio_state_t macio_state_t;
struct macio_state_t { struct macio_state_t {
int is_oldworld; int is_oldworld;
int pic_mem_index; MemoryRegion bar;
int dbdma_mem_index; MemoryRegion *pic_mem;
int cuda_mem_index; MemoryRegion *dbdma_mem;
int escc_mem_index; MemoryRegion *cuda_mem;
MemoryRegion *escc_mem;
void *nvram; void *nvram;
int nb_ide; int nb_ide;
int ide_mem_index[4]; MemoryRegion *ide_mem[4];
}; };
static void macio_map (PCIDevice *pci_dev, int region_num, static void macio_bar_setup(macio_state_t *macio_state)
pcibus_t addr, pcibus_t size, int type)
{ {
macio_state_t *macio_state;
int i; int i;
MemoryRegion *bar = &macio_state->bar;
macio_state = (macio_state_t *)(pci_dev + 1); memory_region_init(bar, "macio", 0x80000);
if (macio_state->pic_mem_index >= 0) { if (macio_state->pic_mem) {
if (macio_state->is_oldworld) { if (macio_state->is_oldworld) {
/* Heathrow PIC */ /* Heathrow PIC */
cpu_register_physical_memory(addr + 0x00000, 0x1000, memory_region_add_subregion(bar, 0x00000, macio_state->pic_mem);
macio_state->pic_mem_index);
} else { } else {
/* OpenPIC */ /* OpenPIC */
cpu_register_physical_memory(addr + 0x40000, 0x40000, memory_region_add_subregion(bar, 0x40000, macio_state->pic_mem);
macio_state->pic_mem_index);
} }
} }
if (macio_state->dbdma_mem_index >= 0) { if (macio_state->dbdma_mem) {
cpu_register_physical_memory(addr + 0x08000, 0x1000, memory_region_add_subregion(bar, 0x08000, macio_state->dbdma_mem);
macio_state->dbdma_mem_index);
} }
if (macio_state->escc_mem_index >= 0) { if (macio_state->escc_mem) {
cpu_register_physical_memory(addr + 0x13000, ESCC_SIZE << 4, memory_region_add_subregion(bar, 0x13000, macio_state->escc_mem);
macio_state->escc_mem_index);
} }
if (macio_state->cuda_mem_index >= 0) { if (macio_state->cuda_mem) {
cpu_register_physical_memory(addr + 0x16000, 0x2000, memory_region_add_subregion(bar, 0x16000, macio_state->cuda_mem);
macio_state->cuda_mem_index);
} }
for (i = 0; i < macio_state->nb_ide; i++) { for (i = 0; i < macio_state->nb_ide; i++) {
if (macio_state->ide_mem_index[i] >= 0) { if (macio_state->ide_mem[i]) {
cpu_register_physical_memory(addr + 0x1f000 + (i * 0x1000), 0x1000, memory_region_add_subregion(bar, 0x1f000 + (i * 0x1000),
macio_state->ide_mem_index[i]); macio_state->ide_mem[i]);
} }
} }
if (macio_state->nvram != NULL) if (macio_state->nvram != NULL)
macio_nvram_map(macio_state->nvram, addr + 0x60000); macio_nvram_setup_bar(macio_state->nvram, bar, 0x60000);
} }
void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index, void macio_init (PCIBus *bus, int device_id, int is_oldworld,
int dbdma_mem_index, int cuda_mem_index, void *nvram, MemoryRegion *pic_mem, MemoryRegion *dbdma_mem,
int nb_ide, int *ide_mem_index, int escc_mem_index) MemoryRegion *cuda_mem, void *nvram,
int nb_ide, MemoryRegion **ide_mem,
MemoryRegion *escc_mem)
{ {
PCIDevice *d; PCIDevice *d;
macio_state_t *macio_state; macio_state_t *macio_state;
@ -92,18 +89,18 @@ void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index,
-1, NULL, NULL); -1, NULL, NULL);
macio_state = (macio_state_t *)(d + 1); macio_state = (macio_state_t *)(d + 1);
macio_state->is_oldworld = is_oldworld; macio_state->is_oldworld = is_oldworld;
macio_state->pic_mem_index = pic_mem_index; macio_state->pic_mem = pic_mem;
macio_state->dbdma_mem_index = dbdma_mem_index; macio_state->dbdma_mem = dbdma_mem;
macio_state->cuda_mem_index = cuda_mem_index; macio_state->cuda_mem = cuda_mem;
macio_state->escc_mem_index = escc_mem_index; macio_state->escc_mem = escc_mem;
macio_state->nvram = nvram; macio_state->nvram = nvram;
if (nb_ide > 4) if (nb_ide > 4)
nb_ide = 4; nb_ide = 4;
macio_state->nb_ide = nb_ide; macio_state->nb_ide = nb_ide;
for (i = 0; i < nb_ide; i++) for (i = 0; i < nb_ide; i++)
macio_state->ide_mem_index[i] = ide_mem_index[i]; macio_state->ide_mem[i] = ide_mem[i];
for (; i < 4; i++) for (; i < 4; i++)
macio_state->ide_mem_index[i] = -1; macio_state->ide_mem[i] = NULL;
/* Note: this code is strongly inspirated from the corresponding code /* Note: this code is strongly inspirated from the corresponding code
in PearPC */ in PearPC */
@ -113,6 +110,7 @@ void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index,
d->config[0x3d] = 0x01; // interrupt on pin 1 d->config[0x3d] = 0x01; // interrupt on pin 1
pci_register_bar(d, 0, 0x80000, macio_bar_setup(macio_state);
PCI_BASE_ADDRESS_SPACE_MEMORY, macio_map); pci_register_bar_region(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
&macio_state->bar);
} }

85
hw/openpic.c
View File

@ -205,7 +205,7 @@ typedef struct IRQ_dst_t {
typedef struct openpic_t { typedef struct openpic_t {
PCIDevice pci_dev; PCIDevice pci_dev;
int mem_index; MemoryRegion mem;
/* Global registers */ /* Global registers */
uint32_t frep; /* Feature reporting register */ uint32_t frep; /* Feature reporting register */
uint32_t glbc; /* Global configuration register */ uint32_t glbc; /* Global configuration register */
@ -984,47 +984,34 @@ static uint32_t openpic_readl (void *opaque,target_phys_addr_t addr)
return retval; return retval;
} }
static CPUWriteMemoryFunc * const openpic_write[] = { static uint64_t openpic_read(void *opaque, target_phys_addr_t addr,
&openpic_buggy_write, unsigned size)
&openpic_buggy_write,
&openpic_writel,
};
static CPUReadMemoryFunc * const openpic_read[] = {
&openpic_buggy_read,
&openpic_buggy_read,
&openpic_readl,
};
static void openpic_map(PCIDevice *pci_dev, int region_num,
pcibus_t addr, pcibus_t size, int type)
{ {
openpic_t *opp; openpic_t *opp = opaque;
DPRINTF("Map OpenPIC\n"); switch (size) {
opp = (openpic_t *)pci_dev; case 4: return openpic_readl(opp, addr);
/* Global registers */ default: return openpic_buggy_read(opp, addr);
DPRINTF("Register OPENPIC gbl %08x => %08x\n", }
addr + 0x1000, addr + 0x1000 + 0x100);
/* Timer registers */
DPRINTF("Register OPENPIC timer %08x => %08x\n",
addr + 0x1100, addr + 0x1100 + 0x40 * MAX_TMR);
/* Interrupt source registers */
DPRINTF("Register OPENPIC src %08x => %08x\n",
addr + 0x10000, addr + 0x10000 + 0x20 * (OPENPIC_EXT_IRQ + 2));
/* Per CPU registers */
DPRINTF("Register OPENPIC dst %08x => %08x\n",
addr + 0x20000, addr + 0x20000 + 0x1000 * MAX_CPU);
cpu_register_physical_memory(addr, 0x40000, opp->mem_index);
#if 0 // Don't implement ISU for now
opp_io_memory = cpu_register_io_memory(openpic_src_read,
openpic_src_write, NULL
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(isu_base, 0x20 * (EXT_IRQ + 2),
opp_io_memory);
#endif
} }
static void openpic_write(void *opaque, target_phys_addr_t addr,
uint64_t data, unsigned size)
{
openpic_t *opp = opaque;
switch (size) {
case 4: return openpic_writel(opp, addr, data);
default: return openpic_buggy_write(opp, addr, data);
}
}
static const MemoryRegionOps openpic_ops = {
.read = openpic_read,
.write = openpic_write,
.endianness = DEVICE_LITTLE_ENDIAN,
};
static void openpic_save_IRQ_queue(QEMUFile* f, IRQ_queue_t *q) static void openpic_save_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
{ {
unsigned int i; unsigned int i;
@ -1161,7 +1148,7 @@ static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src)
qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]); qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
} }
qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus, qemu_irq *openpic_init (PCIBus *bus, MemoryRegion **pmem, int nb_cpus,
qemu_irq **irqs, qemu_irq irq_out) qemu_irq **irqs, qemu_irq irq_out)
{ {
openpic_t *opp; openpic_t *opp;
@ -1180,14 +1167,22 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
pci_config_set_class(pci_conf, PCI_CLASS_SYSTEM_OTHER); // FIXME? pci_config_set_class(pci_conf, PCI_CLASS_SYSTEM_OTHER); // FIXME?
pci_conf[0x3d] = 0x00; // no interrupt pin pci_conf[0x3d] = 0x00; // no interrupt pin
memory_region_init_io(&opp->mem, &openpic_ops, opp, "openpic", 0x40000);
#if 0 // Don't implement ISU for now
opp_io_memory = cpu_register_io_memory(openpic_src_read,
openpic_src_write, NULL
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(isu_base, 0x20 * (EXT_IRQ + 2),
opp_io_memory);
#endif
/* Register I/O spaces */ /* Register I/O spaces */
pci_register_bar(&opp->pci_dev, 0, 0x40000, pci_register_bar_region(&opp->pci_dev, 0,
PCI_BASE_ADDRESS_SPACE_MEMORY, &openpic_map); PCI_BASE_ADDRESS_SPACE_MEMORY, &opp->mem);
} else { } else {
opp = qemu_mallocz(sizeof(openpic_t)); opp = qemu_mallocz(sizeof(openpic_t));
memory_region_init_io(&opp->mem, &openpic_ops, opp, "openpic", 0x40000);
} }
opp->mem_index = cpu_register_io_memory(openpic_read, openpic_write, opp,
DEVICE_LITTLE_ENDIAN);
// isu_base &= 0xFFFC0000; // isu_base &= 0xFFFC0000;
opp->nb_cpus = nb_cpus; opp->nb_cpus = nb_cpus;
@ -1223,8 +1218,8 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
opp->irq_raise = openpic_irq_raise; opp->irq_raise = openpic_irq_raise;
opp->reset = openpic_reset; opp->reset = openpic_reset;
if (pmem_index) if (pmem)
*pmem_index = opp->mem_index; *pmem = &opp->mem;
return qemu_allocate_irqs(openpic_set_irq, opp, opp->max_irq); return qemu_allocate_irqs(openpic_set_irq, opp, opp->max_irq);
} }

2
hw/openpic.h
View File

@ -11,7 +11,7 @@ enum {
OPENPIC_OUTPUT_NB, OPENPIC_OUTPUT_NB,
}; };
qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus, qemu_irq *openpic_init (PCIBus *bus, MemoryRegion **pmem, int nb_cpus,
qemu_irq **irqs, qemu_irq irq_out); qemu_irq **irqs, qemu_irq irq_out);
qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus, qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
qemu_irq **irqs, qemu_irq irq_out); qemu_irq **irqs, qemu_irq irq_out);

16
hw/ppc_mac.h
View File

@ -42,15 +42,16 @@
#define ESCC_CLOCK 3686400 #define ESCC_CLOCK 3686400
/* Cuda */ /* Cuda */
void cuda_init (int *cuda_mem_index, qemu_irq irq); void cuda_init (MemoryRegion **cuda_mem, qemu_irq irq);
/* MacIO */ /* MacIO */
void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index, void macio_init (PCIBus *bus, int device_id, int is_oldworld,
int dbdma_mem_index, int cuda_mem_index, void *nvram, MemoryRegion *pic_mem, MemoryRegion *dbdma_mem,
int nb_ide, int *ide_mem_index, int escc_mem_index); MemoryRegion *cuda_mem, void *nvram,
int nb_ide, MemoryRegion **ide_mem, MemoryRegion *escc_mem);
/* Heathrow PIC */ /* Heathrow PIC */
qemu_irq *heathrow_pic_init(int *pmem_index, qemu_irq *heathrow_pic_init(MemoryRegion **pmem,
int nb_cpus, qemu_irq **irqs); int nb_cpus, qemu_irq **irqs);
/* Grackle PCI */ /* Grackle PCI */
@ -69,9 +70,10 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic,
/* Mac NVRAM */ /* Mac NVRAM */
typedef struct MacIONVRAMState MacIONVRAMState; typedef struct MacIONVRAMState MacIONVRAMState;
MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size, MacIONVRAMState *macio_nvram_init (target_phys_addr_t size,
unsigned int it_shift); unsigned int it_shift);
void macio_nvram_map (void *opaque, target_phys_addr_t mem_base); void macio_nvram_setup_bar(MacIONVRAMState *s, MemoryRegion *bar,
target_phys_addr_t mem_base);
void pmac_format_nvram_partition (MacIONVRAMState *nvr, int len); void pmac_format_nvram_partition (MacIONVRAMState *nvr, int len);
uint32_t macio_nvram_read (void *opaque, uint32_t addr); uint32_t macio_nvram_read (void *opaque, uint32_t addr);
void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val); void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val);

30
hw/ppc_newworld.c
View File

@ -144,10 +144,9 @@ static void ppc_core99_init (ram_addr_t ram_size,
long kernel_size, initrd_size; long kernel_size, initrd_size;
PCIBus *pci_bus; PCIBus *pci_bus;
MacIONVRAMState *nvr; MacIONVRAMState *nvr;
int nvram_mem_index;
int bios_size; int bios_size;
int pic_mem_index, dbdma_mem_index, cuda_mem_index, escc_mem_index; MemoryRegion *pic_mem, *dbdma_mem, *cuda_mem, *escc_mem;
int ide_mem_index[3]; MemoryRegion *ide_mem[3];
int ppc_boot_device; int ppc_boot_device;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
void *fw_cfg; void *fw_cfg;
@ -315,7 +314,7 @@ static void ppc_core99_init (ram_addr_t ram_size,
exit(1); exit(1);
} }
} }
pic = openpic_init(NULL, &pic_mem_index, smp_cpus, openpic_irqs, NULL); pic = openpic_init(NULL, &pic_mem, smp_cpus, openpic_irqs, NULL);
if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) { if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
/* 970 gets a U3 bus */ /* 970 gets a U3 bus */
pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io()); pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io());
@ -327,32 +326,31 @@ static void ppc_core99_init (ram_addr_t ram_size,
/* init basic PC hardware */ /* init basic PC hardware */
pci_vga_init(pci_bus); pci_vga_init(pci_bus);
escc_mem_index = escc_init(0x80013000, pic[0x25], pic[0x24], escc_mem = escc_init(0x80013000, pic[0x25], pic[0x24],
serial_hds[0], serial_hds[1], ESCC_CLOCK, 4); serial_hds[0], serial_hds[1], ESCC_CLOCK, 4);
for(i = 0; i < nb_nics; i++) for(i = 0; i < nb_nics; i++)
pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
ide_drive_get(hd, MAX_IDE_BUS); ide_drive_get(hd, MAX_IDE_BUS);
dbdma = DBDMA_init(&dbdma_mem_index); dbdma = DBDMA_init(&dbdma_mem);
/* We only emulate 2 out of 3 IDE controllers for now */ /* We only emulate 2 out of 3 IDE controllers for now */
ide_mem_index[0] = -1; ide_mem[0] = NULL;
ide_mem_index[1] = pmac_ide_init(hd, pic[0x0d], dbdma, 0x16, pic[0x02]); ide_mem[1] = pmac_ide_init(hd, pic[0x0d], dbdma, 0x16, pic[0x02]);
ide_mem_index[2] = pmac_ide_init(&hd[MAX_IDE_DEVS], pic[0x0e], dbdma, 0x1a, pic[0x02]); ide_mem[2] = pmac_ide_init(&hd[MAX_IDE_DEVS], pic[0x0e], dbdma, 0x1a, pic[0x02]);
/* cuda also initialize ADB */ /* cuda also initialize ADB */
if (machine_arch == ARCH_MAC99_U3) { if (machine_arch == ARCH_MAC99_U3) {
usb_enabled = 1; usb_enabled = 1;
} }
cuda_init(&cuda_mem_index, pic[0x19]); cuda_init(&cuda_mem, pic[0x19]);
adb_kbd_init(&adb_bus); adb_kbd_init(&adb_bus);
adb_mouse_init(&adb_bus); adb_mouse_init(&adb_bus);
macio_init(pci_bus, PCI_DEVICE_ID_APPLE_UNI_N_KEYL, 0, pic_mem_index, macio_init(pci_bus, PCI_DEVICE_ID_APPLE_UNI_N_KEYL, 0, pic_mem,
dbdma_mem_index, cuda_mem_index, NULL, 3, ide_mem_index, dbdma_mem, cuda_mem, NULL, 3, ide_mem, escc_mem);
escc_mem_index);
if (usb_enabled) { if (usb_enabled) {
usb_ohci_init_pci(pci_bus, -1); usb_ohci_init_pci(pci_bus, -1);
@ -369,9 +367,9 @@ static void ppc_core99_init (ram_addr_t ram_size,
graphic_depth = 15; graphic_depth = 15;
/* The NewWorld NVRAM is not located in the MacIO device */ /* The NewWorld NVRAM is not located in the MacIO device */
nvr = macio_nvram_init(&nvram_mem_index, 0x2000, 1); nvr = macio_nvram_init(0x2000, 1);
pmac_format_nvram_partition(nvr, 0x2000); pmac_format_nvram_partition(nvr, 0x2000);
macio_nvram_map(nvr, 0xFFF04000); macio_nvram_setup_bar(nvr, get_system_memory(), 0xFFF04000);
/* No PCI init: the BIOS will do it */ /* No PCI init: the BIOS will do it */
fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);

23
hw/ppc_oldworld.c
View File

@ -82,8 +82,8 @@ static void ppc_heathrow_init (ram_addr_t ram_size,
PCIBus *pci_bus; PCIBus *pci_bus;
MacIONVRAMState *nvr; MacIONVRAMState *nvr;
int bios_size; int bios_size;
int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index; MemoryRegion *pic_mem, *dbdma_mem, *cuda_mem;
int escc_mem_index, ide_mem_index[2]; MemoryRegion *escc_mem, *ide_mem[2];
uint16_t ppc_boot_device; uint16_t ppc_boot_device;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
void *fw_cfg; void *fw_cfg;
@ -233,13 +233,13 @@ static void ppc_heathrow_init (ram_addr_t ram_size,
if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
hw_error("Only 6xx bus is supported on heathrow machine\n"); hw_error("Only 6xx bus is supported on heathrow machine\n");
} }
pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs); pic = heathrow_pic_init(&pic_mem, 1, heathrow_irqs);
pci_bus = pci_grackle_init(0xfec00000, pic, pci_bus = pci_grackle_init(0xfec00000, pic,
get_system_memory(), get_system_memory(),
get_system_io()); get_system_io());
pci_vga_init(pci_bus); pci_vga_init(pci_bus);
escc_mem_index = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0], escc_mem = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0],
serial_hds[1], ESCC_CLOCK, 4); serial_hds[1], ESCC_CLOCK, 4);
for(i = 0; i < nb_nics; i++) for(i = 0; i < nb_nics; i++)
@ -249,9 +249,9 @@ static void ppc_heathrow_init (ram_addr_t ram_size,
ide_drive_get(hd, MAX_IDE_BUS); ide_drive_get(hd, MAX_IDE_BUS);
/* First IDE channel is a MAC IDE on the MacIO bus */ /* First IDE channel is a MAC IDE on the MacIO bus */
dbdma = DBDMA_init(&dbdma_mem_index); dbdma = DBDMA_init(&dbdma_mem);
ide_mem_index[0] = -1; ide_mem[0] = NULL;
ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D], dbdma, 0x16, pic[0x02]); ide_mem[1] = pmac_ide_init(hd, pic[0x0D], dbdma, 0x16, pic[0x02]);
/* Second IDE channel is a CMD646 on the PCI bus */ /* Second IDE channel is a CMD646 on the PCI bus */
hd[0] = hd[MAX_IDE_DEVS]; hd[0] = hd[MAX_IDE_DEVS];
@ -260,17 +260,16 @@ static void ppc_heathrow_init (ram_addr_t ram_size,
pci_cmd646_ide_init(pci_bus, hd, 0); pci_cmd646_ide_init(pci_bus, hd, 0);
/* cuda also initialize ADB */ /* cuda also initialize ADB */
cuda_init(&cuda_mem_index, pic[0x12]); cuda_init(&cuda_mem, pic[0x12]);
adb_kbd_init(&adb_bus); adb_kbd_init(&adb_bus);
adb_mouse_init(&adb_bus); adb_mouse_init(&adb_bus);
nvr = macio_nvram_init(&nvram_mem_index, 0x2000, 4); nvr = macio_nvram_init(0x2000, 4);
pmac_format_nvram_partition(nvr, 0x2000); pmac_format_nvram_partition(nvr, 0x2000);
macio_init(pci_bus, PCI_DEVICE_ID_APPLE_343S1201, 1, pic_mem_index, macio_init(pci_bus, PCI_DEVICE_ID_APPLE_343S1201, 1, pic_mem,
dbdma_mem_index, cuda_mem_index, nvr, 2, ide_mem_index, dbdma_mem, cuda_mem, nvr, 2, ide_mem, escc_mem);
escc_mem_index);
if (usb_enabled) { if (usb_enabled) {
usb_ohci_init_pci(pci_bus, -1); usb_ohci_init_pci(pci_bus, -1);