mirror of https://github.com/proxmox/mirror_qemu
target/openrisc: Restrict cpu_exec_interrupt() handler to sysemu
Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210911165434.531552-17-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>master
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dabfe1332e
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250ae6dfc7
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@ -186,10 +186,10 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = {
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static const struct TCGCPUOps openrisc_tcg_ops = {
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static const struct TCGCPUOps openrisc_tcg_ops = {
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.initialize = openrisc_translate_init,
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.initialize = openrisc_translate_init,
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.cpu_exec_interrupt = openrisc_cpu_exec_interrupt,
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.tlb_fill = openrisc_cpu_tlb_fill,
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.tlb_fill = openrisc_cpu_tlb_fill,
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#ifndef CONFIG_USER_ONLY
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#ifndef CONFIG_USER_ONLY
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.cpu_exec_interrupt = openrisc_cpu_exec_interrupt,
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.do_interrupt = openrisc_cpu_do_interrupt,
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.do_interrupt = openrisc_cpu_do_interrupt,
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#endif /* !CONFIG_USER_ONLY */
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#endif /* !CONFIG_USER_ONLY */
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};
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};
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@ -312,8 +312,6 @@ struct OpenRISCCPU {
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void cpu_openrisc_list(void);
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void cpu_openrisc_list(void);
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void openrisc_cpu_do_interrupt(CPUState *cpu);
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bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req);
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void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
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void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
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hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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@ -331,6 +329,9 @@ int print_insn_or1k(bfd_vma addr, disassemble_info *info);
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#ifndef CONFIG_USER_ONLY
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#ifndef CONFIG_USER_ONLY
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extern const VMStateDescription vmstate_openrisc_cpu;
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extern const VMStateDescription vmstate_openrisc_cpu;
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void openrisc_cpu_do_interrupt(CPUState *cpu);
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bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req);
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/* hw/openrisc_pic.c */
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/* hw/openrisc_pic.c */
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void cpu_openrisc_pic_init(OpenRISCCPU *cpu);
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void cpu_openrisc_pic_init(OpenRISCCPU *cpu);
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@ -28,7 +28,6 @@
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void openrisc_cpu_do_interrupt(CPUState *cs)
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void openrisc_cpu_do_interrupt(CPUState *cs)
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{
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{
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#ifndef CONFIG_USER_ONLY
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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CPUOpenRISCState *env = &cpu->env;
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CPUOpenRISCState *env = &cpu->env;
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int exception = cs->exception_index;
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int exception = cs->exception_index;
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@ -96,7 +95,6 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
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} else {
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} else {
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cpu_abort(cs, "Unhandled exception 0x%x\n", exception);
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cpu_abort(cs, "Unhandled exception 0x%x\n", exception);
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}
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}
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#endif
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cs->exception_index = -1;
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cs->exception_index = -1;
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}
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}
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@ -9,7 +9,6 @@ openrisc_ss.add(files(
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'exception_helper.c',
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'exception_helper.c',
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'fpu_helper.c',
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'fpu_helper.c',
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'gdbstub.c',
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'gdbstub.c',
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'interrupt.c',
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'interrupt_helper.c',
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'interrupt_helper.c',
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'mmu.c',
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'mmu.c',
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'sys_helper.c',
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'sys_helper.c',
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@ -17,7 +16,10 @@ openrisc_ss.add(files(
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))
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))
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openrisc_softmmu_ss = ss.source_set()
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openrisc_softmmu_ss = ss.source_set()
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openrisc_softmmu_ss.add(files('machine.c'))
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openrisc_softmmu_ss.add(files(
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'interrupt.c',
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'machine.c',
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))
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target_arch += {'openrisc': openrisc_ss}
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target_arch += {'openrisc': openrisc_ss}
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target_softmmu_arch += {'openrisc': openrisc_softmmu_ss}
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target_softmmu_arch += {'openrisc': openrisc_softmmu_ss}
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