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Convert most env fields to TCG registers 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5176 c046a42c-6fe2-441c-8c8c-71466251a162
master
blueswir1 2008-09-06 17:51:43 +00:00
parent 47ad35f16a
commit 255e1fcb5a
1 changed files with 91 additions and 95 deletions
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186
target-sparc/translate.c
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@ -41,9 +41,17 @@
static TCGv cpu_env, cpu_regwptr; static TCGv cpu_env, cpu_regwptr;
static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst; static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8]; static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
static TCGv cpu_y;
#ifndef CONFIG_USER_ONLY
static TCGv cpu_tbr;
#endif
static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val; static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
#ifdef TARGET_SPARC64 #ifdef TARGET_SPARC64
static TCGv cpu_xcc; static TCGv cpu_xcc, cpu_asi, cpu_fprs, cpu_gsr;
static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
#else
static TCGv cpu_wim;
#endif #endif
/* local register indexes (only used inside old micro ops) */ /* local register indexes (only used inside old micro ops) */
static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64; static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
@ -724,8 +732,7 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
T1 = 0; T1 = 0;
*/ */
tcg_gen_mov_tl(cpu_cc_src, src1); tcg_gen_mov_tl(cpu_cc_src, src1);
tcg_gen_ld_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y)); tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
tcg_gen_andi_tl(r_temp, r_temp, 0x1);
tcg_gen_mov_tl(cpu_cc_src2, src2); tcg_gen_mov_tl(cpu_cc_src2, src2);
tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1); tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
tcg_gen_movi_tl(cpu_cc_src2, 0); tcg_gen_movi_tl(cpu_cc_src2, 0);
@ -735,10 +742,8 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
// env->y = (b2 << 31) | (env->y >> 1); // env->y = (b2 << 31) | (env->y >> 1);
tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1); tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
tcg_gen_shli_tl(r_temp, r_temp, 31); tcg_gen_shli_tl(r_temp, r_temp, 31);
tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y)); tcg_gen_shri_tl(cpu_tmp0, cpu_y, 1);
tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 1); tcg_gen_or_tl(cpu_y, cpu_tmp0, r_temp);
tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, r_temp);
tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y));
// b1 = N ^ V; // b1 = N ^ V;
gen_mov_reg_N(cpu_tmp0, cpu_psr); gen_mov_reg_N(cpu_tmp0, cpu_psr);
@ -776,8 +781,7 @@ static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
tcg_gen_shri_i64(r_temp, r_temp2, 32); tcg_gen_shri_i64(r_temp, r_temp2, 32);
tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp); tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp);
tcg_temp_free(r_temp); tcg_temp_free(r_temp);
tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff); tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y));
#ifdef TARGET_SPARC64 #ifdef TARGET_SPARC64
tcg_gen_mov_i64(dst, r_temp2); tcg_gen_mov_i64(dst, r_temp2);
#else #else
@ -800,8 +804,7 @@ static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
tcg_gen_shri_i64(r_temp, r_temp2, 32); tcg_gen_shri_i64(r_temp, r_temp2, 32);
tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp); tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp);
tcg_temp_free(r_temp); tcg_temp_free(r_temp);
tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff); tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y));
#ifdef TARGET_SPARC64 #ifdef TARGET_SPARC64
tcg_gen_mov_i64(dst, r_temp2); tcg_gen_mov_i64(dst, r_temp2);
#else #else
@ -1645,7 +1648,7 @@ static inline TCGv gen_get_asi(int insn, TCGv r_addr)
if (IS_IMM) { if (IS_IMM) {
r_asi = tcg_temp_new(TCG_TYPE_I32); r_asi = tcg_temp_new(TCG_TYPE_I32);
tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi)); tcg_gen_mov_i32(r_asi, cpu_asi);
} else { } else {
asi = GET_FIELD(insn, 19, 26); asi = GET_FIELD(insn, 19, 26);
r_asi = tcg_const_i32(asi); r_asi = tcg_const_i32(asi);
@ -2080,9 +2083,7 @@ static void disas_sparc_insn(DisasContext * dc)
SPARCv8 manual, rdy on the SPARCv8 manual, rdy on the
microSPARC II */ microSPARC II */
#endif #endif
tcg_gen_ld_tl(cpu_tmp0, cpu_env, gen_movl_TN_reg(rd, cpu_y);
offsetof(CPUSPARCState, y));
gen_movl_TN_reg(rd, cpu_tmp0);
break; break;
#ifdef TARGET_SPARC64 #ifdef TARGET_SPARC64
case 0x2: /* V9 rdccr */ case 0x2: /* V9 rdccr */
@ -2090,9 +2091,7 @@ static void disas_sparc_insn(DisasContext * dc)
gen_movl_TN_reg(rd, cpu_dst); gen_movl_TN_reg(rd, cpu_dst);
break; break;
case 0x3: /* V9 rdasi */ case 0x3: /* V9 rdasi */
tcg_gen_ld_i32(cpu_tmp32, cpu_env, tcg_gen_ext_i32_tl(cpu_dst, cpu_asi);
offsetof(CPUSPARCState, asi));
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
gen_movl_TN_reg(rd, cpu_dst); gen_movl_TN_reg(rd, cpu_dst);
break; break;
case 0x4: /* V9 rdtick */ case 0x4: /* V9 rdtick */
@ -2118,9 +2117,7 @@ static void disas_sparc_insn(DisasContext * dc)
} }
break; break;
case 0x6: /* V9 rdfprs */ case 0x6: /* V9 rdfprs */
tcg_gen_ld_i32(cpu_tmp32, cpu_env, tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs);
offsetof(CPUSPARCState, fprs));
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
gen_movl_TN_reg(rd, cpu_dst); gen_movl_TN_reg(rd, cpu_dst);
break; break;
case 0xf: /* V9 membar */ case 0xf: /* V9 membar */
@ -2128,14 +2125,10 @@ static void disas_sparc_insn(DisasContext * dc)
case 0x13: /* Graphics Status */ case 0x13: /* Graphics Status */
if (gen_trap_ifnofpu(dc, cpu_cond)) if (gen_trap_ifnofpu(dc, cpu_cond))
goto jmp_insn; goto jmp_insn;
tcg_gen_ld_tl(cpu_tmp0, cpu_env, gen_movl_TN_reg(rd, cpu_gsr);
offsetof(CPUSPARCState, gsr));
gen_movl_TN_reg(rd, cpu_tmp0);
break; break;
case 0x17: /* Tick compare */ case 0x17: /* Tick compare */
tcg_gen_ld_tl(cpu_tmp0, cpu_env, gen_movl_TN_reg(rd, cpu_tick_cmpr);
offsetof(CPUSPARCState, tick_cmpr));
gen_movl_TN_reg(rd, cpu_tmp0);
break; break;
case 0x18: /* System tick */ case 0x18: /* System tick */
{ {
@ -2151,9 +2144,7 @@ static void disas_sparc_insn(DisasContext * dc)
} }
break; break;
case 0x19: /* System tick compare */ case 0x19: /* System tick compare */
tcg_gen_ld_tl(cpu_tmp0, cpu_env, gen_movl_TN_reg(rd, cpu_stick_cmpr);
offsetof(CPUSPARCState, stick_cmpr));
gen_movl_TN_reg(rd, cpu_tmp0);
break; break;
case 0x10: /* Performance Control */ case 0x10: /* Performance Control */
case 0x11: /* Performance Instrumentation Counter */ case 0x11: /* Performance Instrumentation Counter */
@ -2184,23 +2175,16 @@ static void disas_sparc_insn(DisasContext * dc)
// gen_op_rdhtstate(); // gen_op_rdhtstate();
break; break;
case 3: // hintp case 3: // hintp
tcg_gen_ld_i32(cpu_tmp32, cpu_env, tcg_gen_mov_tl(cpu_dst, cpu_hintp);
offsetof(CPUSPARCState, hintp));
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
break; break;
case 5: // htba case 5: // htba
tcg_gen_ld_i32(cpu_tmp32, cpu_env, tcg_gen_mov_tl(cpu_dst, cpu_htba);
offsetof(CPUSPARCState, htba));
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
break; break;
case 6: // hver case 6: // hver
tcg_gen_ld_i32(cpu_tmp32, cpu_env, tcg_gen_mov_tl(cpu_dst, cpu_hver);
offsetof(CPUSPARCState, hver));
tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
break; break;
case 31: // hstick_cmpr case 31: // hstick_cmpr
tcg_gen_ld_tl(cpu_dst, cpu_env, tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr);
offsetof(CPUSPARCState, hstick_cmpr));
break; break;
default: default:
goto illegal_insn; goto illegal_insn;
@ -2276,8 +2260,7 @@ static void disas_sparc_insn(DisasContext * dc)
} }
break; break;
case 5: // tba case 5: // tba
tcg_gen_ld_tl(cpu_tmp0, cpu_env, tcg_gen_mov_tl(cpu_tmp0, cpu_tbr);
offsetof(CPUSPARCState, tbr));
break; break;
case 6: // pstate case 6: // pstate
tcg_gen_ld_i32(cpu_tmp32, cpu_env, tcg_gen_ld_i32(cpu_tmp32, cpu_env,
@ -2332,22 +2315,17 @@ static void disas_sparc_insn(DisasContext * dc)
CHECK_IU_FEATURE(dc, HYPV); CHECK_IU_FEATURE(dc, HYPV);
if (!hypervisor(dc)) if (!hypervisor(dc))
goto priv_insn; goto priv_insn;
tcg_gen_ld_i32(cpu_tmp32, cpu_env, tcg_gen_ext_i32_tl(cpu_tmp0, cpu_ssr);
offsetof(CPUSPARCState, ssr));
tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
break; break;
case 31: // ver case 31: // ver
tcg_gen_ld_tl(cpu_tmp0, cpu_env, tcg_gen_mov_tl(cpu_tmp0, cpu_ver);
offsetof(CPUSPARCState, version));
break; break;
case 15: // fq case 15: // fq
default: default:
goto illegal_insn; goto illegal_insn;
} }
#else #else
tcg_gen_ld_i32(cpu_tmp32, cpu_env, tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim);
offsetof(CPUSPARCState, wim));
tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
#endif #endif
gen_movl_TN_reg(rd, cpu_tmp0); gen_movl_TN_reg(rd, cpu_tmp0);
break; break;
@ -2358,8 +2336,7 @@ static void disas_sparc_insn(DisasContext * dc)
#else #else
if (!supervisor(dc)) if (!supervisor(dc))
goto priv_insn; goto priv_insn;
tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, tbr)); gen_movl_TN_reg(rd, cpu_tbr);
gen_movl_TN_reg(rd, cpu_tmp0);
#endif #endif
break; break;
#endif #endif
@ -3152,9 +3129,7 @@ static void disas_sparc_insn(DisasContext * dc)
{ {
switch(rd) { switch(rd) {
case 0: /* wry */ case 0: /* wry */
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); tcg_gen_xor_tl(cpu_y, cpu_src1, cpu_src2);
tcg_gen_st_tl(cpu_tmp0, cpu_env,
offsetof(CPUSPARCState, y));
break; break;
#ifndef TARGET_SPARC64 #ifndef TARGET_SPARC64
case 0x01 ... 0x0f: /* undefined in the case 0x01 ... 0x0f: /* undefined in the
@ -3173,15 +3148,11 @@ static void disas_sparc_insn(DisasContext * dc)
break; break;
case 0x3: /* V9 wrasi */ case 0x3: /* V9 wrasi */
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); tcg_gen_trunc_tl_i32(cpu_asi, cpu_dst);
tcg_gen_st_i32(cpu_tmp32, cpu_env,
offsetof(CPUSPARCState, asi));
break; break;
case 0x6: /* V9 wrfprs */ case 0x6: /* V9 wrfprs */
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); tcg_gen_trunc_tl_i32(cpu_fprs, cpu_dst);
tcg_gen_st_i32(cpu_tmp32, cpu_env,
offsetof(CPUSPARCState, fprs));
save_state(dc, cpu_cond); save_state(dc, cpu_cond);
gen_op_next_insn(); gen_op_next_insn();
tcg_gen_exit_tb(0); tcg_gen_exit_tb(0);
@ -3196,9 +3167,7 @@ static void disas_sparc_insn(DisasContext * dc)
case 0x13: /* Graphics Status */ case 0x13: /* Graphics Status */
if (gen_trap_ifnofpu(dc, cpu_cond)) if (gen_trap_ifnofpu(dc, cpu_cond))
goto jmp_insn; goto jmp_insn;
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2);
tcg_gen_st_tl(cpu_tmp0, cpu_env,
offsetof(CPUSPARCState, gsr));
break; break;
case 0x17: /* Tick compare */ case 0x17: /* Tick compare */
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
@ -3208,16 +3177,13 @@ static void disas_sparc_insn(DisasContext * dc)
{ {
TCGv r_tickptr; TCGv r_tickptr;
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1,
cpu_src2); cpu_src2);
tcg_gen_st_tl(cpu_tmp0, cpu_env,
offsetof(CPUSPARCState,
tick_cmpr));
r_tickptr = tcg_temp_new(TCG_TYPE_PTR); r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
tcg_gen_ld_ptr(r_tickptr, cpu_env, tcg_gen_ld_ptr(r_tickptr, cpu_env,
offsetof(CPUState, tick)); offsetof(CPUState, tick));
tcg_gen_helper_0_2(helper_tick_set_limit, tcg_gen_helper_0_2(helper_tick_set_limit,
r_tickptr, cpu_tmp0); r_tickptr, cpu_tick_cmpr);
tcg_temp_free(r_tickptr); tcg_temp_free(r_tickptr);
} }
break; break;
@ -3247,16 +3213,13 @@ static void disas_sparc_insn(DisasContext * dc)
{ {
TCGv r_tickptr; TCGv r_tickptr;
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1,
cpu_src2); cpu_src2);
tcg_gen_st_tl(cpu_tmp0, cpu_env,
offsetof(CPUSPARCState,
stick_cmpr));
r_tickptr = tcg_temp_new(TCG_TYPE_PTR); r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
tcg_gen_ld_ptr(r_tickptr, cpu_env, tcg_gen_ld_ptr(r_tickptr, cpu_env,
offsetof(CPUState, stick)); offsetof(CPUState, stick));
tcg_gen_helper_0_2(helper_tick_set_limit, tcg_gen_helper_0_2(helper_tick_set_limit,
r_tickptr, cpu_tmp0); r_tickptr, cpu_stick_cmpr);
tcg_temp_free(r_tickptr); tcg_temp_free(r_tickptr);
} }
break; break;
@ -3374,8 +3337,7 @@ static void disas_sparc_insn(DisasContext * dc)
} }
break; break;
case 5: // tba case 5: // tba
tcg_gen_st_tl(cpu_tmp0, cpu_env, tcg_gen_mov_tl(cpu_tbr, cpu_tmp0);
offsetof(CPUSPARCState, tbr));
break; break;
case 6: // pstate case 6: // pstate
save_state(dc, cpu_cond); save_state(dc, cpu_cond);
@ -3438,9 +3400,7 @@ static void disas_sparc_insn(DisasContext * dc)
CHECK_IU_FEATURE(dc, HYPV); CHECK_IU_FEATURE(dc, HYPV);
if (!hypervisor(dc)) if (!hypervisor(dc))
goto priv_insn; goto priv_insn;
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); tcg_gen_trunc_tl_i32(cpu_ssr, cpu_tmp0);
tcg_gen_st_i32(cpu_tmp32, cpu_env,
offsetof(CPUSPARCState, ssr));
break; break;
default: default:
goto illegal_insn; goto illegal_insn;
@ -3450,8 +3410,7 @@ static void disas_sparc_insn(DisasContext * dc)
if (dc->def->nwindows != 32) if (dc->def->nwindows != 32)
tcg_gen_andi_tl(cpu_tmp32, cpu_tmp32, tcg_gen_andi_tl(cpu_tmp32, cpu_tmp32,
(1 << dc->def->nwindows) - 1); (1 << dc->def->nwindows) - 1);
tcg_gen_st_i32(cpu_tmp32, cpu_env, tcg_gen_mov_i32(cpu_wim, cpu_tmp32);
offsetof(CPUSPARCState, wim));
#endif #endif
} }
break; break;
@ -3460,9 +3419,7 @@ static void disas_sparc_insn(DisasContext * dc)
#ifndef TARGET_SPARC64 #ifndef TARGET_SPARC64
if (!supervisor(dc)) if (!supervisor(dc))
goto priv_insn; goto priv_insn;
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2);
tcg_gen_st_tl(cpu_tmp0, cpu_env,
offsetof(CPUSPARCState, tbr));
#else #else
CHECK_IU_FEATURE(dc, HYPV); CHECK_IU_FEATURE(dc, HYPV);
if (!hypervisor(dc)) if (!hypervisor(dc))
@ -3480,27 +3437,21 @@ static void disas_sparc_insn(DisasContext * dc)
// XXX gen_op_wrhtstate(); // XXX gen_op_wrhtstate();
break; break;
case 3: // hintp case 3: // hintp
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); tcg_gen_mov_tl(cpu_hintp, cpu_tmp0);
tcg_gen_st_i32(cpu_tmp32, cpu_env,
offsetof(CPUSPARCState, hintp));
break; break;
case 5: // htba case 5: // htba
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); tcg_gen_mov_tl(cpu_htba, cpu_tmp0);
tcg_gen_st_i32(cpu_tmp32, cpu_env,
offsetof(CPUSPARCState, htba));
break; break;
case 31: // hstick_cmpr case 31: // hstick_cmpr
{ {
TCGv r_tickptr; TCGv r_tickptr;
tcg_gen_st_tl(cpu_tmp0, cpu_env, tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0);
offsetof(CPUSPARCState,
hstick_cmpr));
r_tickptr = tcg_temp_new(TCG_TYPE_PTR); r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
tcg_gen_ld_ptr(r_tickptr, cpu_env, tcg_gen_ld_ptr(r_tickptr, cpu_env,
offsetof(CPUState, hstick)); offsetof(CPUState, hstick));
tcg_gen_helper_0_2(helper_tick_set_limit, tcg_gen_helper_0_2(helper_tick_set_limit,
r_tickptr, cpu_tmp0); r_tickptr, cpu_hstick_cmpr);
tcg_temp_free(r_tickptr); tcg_temp_free(r_tickptr);
} }
break; break;
@ -4905,6 +4856,44 @@ void gen_intermediate_code_init(CPUSPARCState *env)
cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32, cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
TCG_AREG0, offsetof(CPUState, xcc), TCG_AREG0, offsetof(CPUState, xcc),
"xcc"); "xcc");
cpu_asi = tcg_global_mem_new(TCG_TYPE_I32,
TCG_AREG0, offsetof(CPUState, asi),
"asi");
cpu_fprs = tcg_global_mem_new(TCG_TYPE_I32,
TCG_AREG0, offsetof(CPUState, fprs),
"fprs");
cpu_gsr = tcg_global_mem_new(TCG_TYPE_TL,
TCG_AREG0, offsetof(CPUState, gsr),
"gsr");
cpu_tick_cmpr = tcg_global_mem_new(TCG_TYPE_TL,
TCG_AREG0,
offsetof(CPUState, tick_cmpr),
"tick_cmpr");
cpu_stick_cmpr = tcg_global_mem_new(TCG_TYPE_TL,
TCG_AREG0,
offsetof(CPUState, stick_cmpr),
"stick_cmpr");
cpu_hstick_cmpr = tcg_global_mem_new(TCG_TYPE_TL,
TCG_AREG0,
offsetof(CPUState, hstick_cmpr),
"hstick_cmpr");
cpu_hintp = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
offsetof(CPUState, hintp),
"hintp");
cpu_htba = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
offsetof(CPUState, htba),
"htba");
cpu_hver = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
offsetof(CPUState, hver),
"hver");
cpu_ssr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
offsetof(CPUState, ssr), "ssr");
cpu_ver = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
offsetof(CPUState, version), "ver");
#else
cpu_wim = tcg_global_mem_new(TCG_TYPE_I32,
TCG_AREG0, offsetof(CPUState, wim),
"wim");
#endif #endif
cpu_cond = tcg_global_mem_new(TCG_TYPE_TL, cpu_cond = tcg_global_mem_new(TCG_TYPE_TL,
TCG_AREG0, offsetof(CPUState, cond), TCG_AREG0, offsetof(CPUState, cond),
@ -4930,6 +4919,13 @@ void gen_intermediate_code_init(CPUSPARCState *env)
cpu_npc = tcg_global_mem_new(TCG_TYPE_TL, cpu_npc = tcg_global_mem_new(TCG_TYPE_TL,
TCG_AREG0, offsetof(CPUState, npc), TCG_AREG0, offsetof(CPUState, npc),
"npc"); "npc");
cpu_y = tcg_global_mem_new(TCG_TYPE_TL,
TCG_AREG0, offsetof(CPUState, y), "y");
#ifndef CONFIG_USER_ONLY
cpu_tbr = tcg_global_mem_new(TCG_TYPE_TL,
TCG_AREG0, offsetof(CPUState, tbr),
"tbr");
#endif
for (i = 1; i < 8; i++) for (i = 1; i < 8; i++)
cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
offsetof(CPUState, gregs[i]), offsetof(CPUState, gregs[i]),