mirror of https://github.com/proxmox/mirror_qemu
target-arm: Use setcond and movcond for csel
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1441909103-24666-5-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>master
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9305eac09e
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259cb68491
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@ -167,6 +167,31 @@ void gen_a64_set_pc_im(uint64_t val)
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tcg_gen_movi_i64(cpu_pc, val);
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}
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typedef struct DisasCompare64 {
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TCGCond cond;
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TCGv_i64 value;
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} DisasCompare64;
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static void a64_test_cc(DisasCompare64 *c64, int cc)
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{
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DisasCompare c32;
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arm_test_cc(&c32, cc);
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/* Sign-extend the 32-bit value so that the GE/LT comparisons work
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* properly. The NE/EQ comparisons are also fine with this choice. */
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c64->cond = c32.cond;
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c64->value = tcg_temp_new_i64();
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tcg_gen_ext_i32_i64(c64->value, c32.value);
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arm_free_cc(&c32);
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}
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static void a64_free_cc(DisasCompare64 *c64)
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{
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tcg_temp_free_i64(c64->value);
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}
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static void gen_exception_internal(int excp)
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{
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TCGv_i32 tcg_excp = tcg_const_i32(excp);
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@ -3607,7 +3632,8 @@ static void disas_cc(DisasContext *s, uint32_t insn)
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static void disas_cond_select(DisasContext *s, uint32_t insn)
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{
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unsigned int sf, else_inv, rm, cond, else_inc, rn, rd;
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TCGv_i64 tcg_rd, tcg_src;
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TCGv_i64 tcg_rd, zero;
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DisasCompare64 c;
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if (extract32(insn, 29, 1) || extract32(insn, 11, 1)) {
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/* S == 1 or op2<1> == 1 */
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@ -3622,49 +3648,36 @@ static void disas_cond_select(DisasContext *s, uint32_t insn)
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rn = extract32(insn, 5, 5);
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rd = extract32(insn, 0, 5);
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if (rd == 31) {
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/* silly no-op write; until we use movcond we must special-case
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* this to avoid a dead temporary across basic blocks.
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*/
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return;
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}
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tcg_rd = cpu_reg(s, rd);
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if (cond >= 0x0e) { /* condition "always" */
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tcg_src = read_cpu_reg(s, rn, sf);
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tcg_gen_mov_i64(tcg_rd, tcg_src);
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} else {
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/* OPTME: we could use movcond here, at the cost of duplicating
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* a lot of the arm_gen_test_cc() logic.
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*/
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TCGLabel *label_match = gen_new_label();
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TCGLabel *label_continue = gen_new_label();
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a64_test_cc(&c, cond);
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zero = tcg_const_i64(0);
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arm_gen_test_cc(cond, label_match);
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/* nomatch: */
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tcg_src = cpu_reg(s, rm);
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if (else_inv && else_inc) {
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tcg_gen_neg_i64(tcg_rd, tcg_src);
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} else if (else_inv) {
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tcg_gen_not_i64(tcg_rd, tcg_src);
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} else if (else_inc) {
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tcg_gen_addi_i64(tcg_rd, tcg_src, 1);
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} else {
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tcg_gen_mov_i64(tcg_rd, tcg_src);
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if (rn == 31 && rm == 31 && (else_inc ^ else_inv)) {
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/* CSET & CSETM. */
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tcg_gen_setcond_i64(tcg_invert_cond(c.cond), tcg_rd, c.value, zero);
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if (else_inv) {
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tcg_gen_neg_i64(tcg_rd, tcg_rd);
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}
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} else {
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TCGv_i64 t_true = cpu_reg(s, rn);
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TCGv_i64 t_false = read_cpu_reg(s, rm, 1);
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if (else_inv && else_inc) {
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tcg_gen_neg_i64(t_false, t_false);
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} else if (else_inv) {
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tcg_gen_not_i64(t_false, t_false);
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} else if (else_inc) {
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tcg_gen_addi_i64(t_false, t_false, 1);
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}
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tcg_gen_movcond_i64(c.cond, tcg_rd, c.value, zero, t_true, t_false);
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}
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tcg_temp_free_i64(zero);
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a64_free_cc(&c);
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if (!sf) {
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tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
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}
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tcg_gen_br(label_continue);
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/* match: */
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gen_set_label(label_match);
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tcg_src = read_cpu_reg(s, rn, sf);
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tcg_gen_mov_i64(tcg_rd, tcg_src);
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/* continue: */
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gen_set_label(label_continue);
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}
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}
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static void handle_clz(DisasContext *s, unsigned int sf,
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