mirror of https://github.com/proxmox/mirror_qemu
acpi: arm/virt: convert build_iort() to endian agnostic build_append_FOO() API
Drop usage of packed structures and explicit endian conversions when building IORT table use endian agnostic build_append_int_noprefix() API to build it. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20210924122802.1455362-30-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com>master
Igor Mammedov
Michael S. Tsirkin
parent
3548494e49
commit
271cbb2f2b
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@ -240,6 +240,28 @@ static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms)
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}
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#endif
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#define ID_MAPPING_ENTRY_SIZE 20
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#define SMMU_V3_ENTRY_SIZE 60
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#define ROOT_COMPLEX_ENTRY_SIZE 32
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#define IORT_NODE_OFFSET 48
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static void build_iort_id_mapping(GArray *table_data, uint32_t input_base,
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uint32_t id_count, uint32_t out_ref)
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{
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/* Identity RID mapping covering the whole input RID range */
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build_append_int_noprefix(table_data, input_base, 4); /* Input base */
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build_append_int_noprefix(table_data, id_count, 4); /* Number of IDs */
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build_append_int_noprefix(table_data, input_base, 4); /* Output base */
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build_append_int_noprefix(table_data, out_ref, 4); /* Output Reference */
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build_append_int_noprefix(table_data, 0, 4); /* Flags */
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}
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struct AcpiIortIdMapping {
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uint32_t input_base;
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uint32_t id_count;
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};
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typedef struct AcpiIortIdMapping AcpiIortIdMapping;
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/* Build the iort ID mapping to SMMUv3 for a given PCI host bridge */
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static int
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iort_host_bridges(Object *obj, void *opaque)
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@ -282,17 +304,16 @@ static void
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build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
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{
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int i, nb_nodes, rc_mapping_count;
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AcpiIortIdMapping *idmap;
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AcpiIortItsGroup *its;
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AcpiIortSmmu3 *smmu;
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AcpiIortRC *rc;
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const uint32_t iort_node_offset = 48;
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const uint32_t iort_node_offset = IORT_NODE_OFFSET;
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size_t node_size, smmu_offset = 0;
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AcpiIortIdMapping *idmap;
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GArray *smmu_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping));
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GArray *its_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping));
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AcpiTable table = { .sig = "IORT", .rev = 0, .oem_id = vms->oem_id,
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.oem_table_id = vms->oem_table_id };
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/* Table 2 The IORT */
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acpi_table_begin(&table, table_data);
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if (vms->iommu == VIRT_IOMMU_SMMUV3) {
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AcpiIortIdMapping next_range = {0};
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@ -330,100 +351,101 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
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nb_nodes = 2; /* RC, ITS */
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rc_mapping_count = 1;
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}
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/* Table 2 The IORT */
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acpi_table_begin(&table, table_data);
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/* Number of IORT Nodes */
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build_append_int_noprefix(table_data, nb_nodes, 4);
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/* Offset to Array of IORT Nodes */
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build_append_int_noprefix(table_data, iort_node_offset, 4);
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build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4);
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build_append_int_noprefix(table_data, 0, 4); /* Reserved */
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/* ITS group node */
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node_size = sizeof(*its) + sizeof(uint32_t);
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its = acpi_data_push(table_data, node_size);
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its->type = ACPI_IORT_NODE_ITS_GROUP;
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its->length = cpu_to_le16(node_size);
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its->its_count = cpu_to_le32(1);
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its->identifiers[0] = 0; /* MADT translation_id */
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/* 3.1.1.3 ITS group node */
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build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Type */
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node_size = 20 /* fixed header size */ + 4 /* 1 GIC ITS Identifier */;
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build_append_int_noprefix(table_data, node_size, 2); /* Length */
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build_append_int_noprefix(table_data, 0, 1); /* Revision */
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build_append_int_noprefix(table_data, 0, 4); /* Reserved */
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build_append_int_noprefix(table_data, 0, 4); /* Number of ID mappings */
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build_append_int_noprefix(table_data, 0, 4); /* Reference to ID Array */
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build_append_int_noprefix(table_data, 1, 4); /* Number of ITSs */
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/* GIC ITS Identifier Array */
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build_append_int_noprefix(table_data, 0 /* MADT translation_id */, 4);
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if (vms->iommu == VIRT_IOMMU_SMMUV3) {
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int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE;
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/* SMMUv3 node */
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smmu_offset = iort_node_offset + node_size;
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node_size = sizeof(*smmu) + sizeof(*idmap);
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smmu = acpi_data_push(table_data, node_size);
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smmu_offset = table_data->len - table.table_offset;
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/* 3.1.1.2 SMMUv3 */
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build_append_int_noprefix(table_data, 4 /* SMMUv3 */, 1); /* Type */
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node_size = SMMU_V3_ENTRY_SIZE + ID_MAPPING_ENTRY_SIZE;
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build_append_int_noprefix(table_data, node_size, 2); /* Length */
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build_append_int_noprefix(table_data, 0, 1); /* Revision */
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build_append_int_noprefix(table_data, 0, 4); /* Reserved */
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build_append_int_noprefix(table_data, 1, 4); /* Number of ID mappings */
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/* Reference to ID Array */
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build_append_int_noprefix(table_data, SMMU_V3_ENTRY_SIZE, 4);
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/* Base address */
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build_append_int_noprefix(table_data, vms->memmap[VIRT_SMMU].base, 8);
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/* Flags */
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build_append_int_noprefix(table_data, 1 /* COHACC OverrideNote */, 4);
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build_append_int_noprefix(table_data, 0, 4); /* Reserved */
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build_append_int_noprefix(table_data, 0, 8); /* VATOS address */
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/* Model */
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build_append_int_noprefix(table_data, 0 /* Generic SMMU-v3 */, 4);
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build_append_int_noprefix(table_data, irq, 4); /* Event */
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build_append_int_noprefix(table_data, irq + 1, 4); /* PRI */
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build_append_int_noprefix(table_data, irq + 3, 4); /* GERR */
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build_append_int_noprefix(table_data, irq + 2, 4); /* Sync */
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smmu->type = ACPI_IORT_NODE_SMMU_V3;
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smmu->length = cpu_to_le16(node_size);
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smmu->mapping_count = cpu_to_le32(1);
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smmu->mapping_offset = cpu_to_le32(sizeof(*smmu));
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smmu->base_address = cpu_to_le64(vms->memmap[VIRT_SMMU].base);
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smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE);
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smmu->event_gsiv = cpu_to_le32(irq);
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smmu->pri_gsiv = cpu_to_le32(irq + 1);
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smmu->sync_gsiv = cpu_to_le32(irq + 2);
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smmu->gerr_gsiv = cpu_to_le32(irq + 3);
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/* Identity RID mapping covering the whole input RID range */
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idmap = &smmu->id_mapping_array[0];
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idmap->input_base = 0;
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idmap->id_count = cpu_to_le32(0xFFFF);
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idmap->output_base = 0;
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/* output IORT node is the ITS group node (the first node) */
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idmap->output_reference = cpu_to_le32(iort_node_offset);
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build_iort_id_mapping(table_data, 0, 0xFFFF, IORT_NODE_OFFSET);
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}
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/* Root Complex Node */
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node_size = sizeof(*rc) + sizeof(*idmap) * rc_mapping_count;
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rc = acpi_data_push(table_data, node_size);
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/* Table 16 Root Complex Node */
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build_append_int_noprefix(table_data, 2 /* Root complex */, 1); /* Type */
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node_size = ROOT_COMPLEX_ENTRY_SIZE +
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ID_MAPPING_ENTRY_SIZE * rc_mapping_count;
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build_append_int_noprefix(table_data, node_size, 2); /* Length */
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build_append_int_noprefix(table_data, 0, 1); /* Revision */
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build_append_int_noprefix(table_data, 0, 4); /* Reserved */
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/* Number of ID mappings */
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build_append_int_noprefix(table_data, rc_mapping_count, 4);
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/* Reference to ID Array */
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build_append_int_noprefix(table_data, ROOT_COMPLEX_ENTRY_SIZE, 4);
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rc->type = ACPI_IORT_NODE_PCI_ROOT_COMPLEX;
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rc->length = cpu_to_le16(node_size);
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rc->mapping_count = cpu_to_le32(rc_mapping_count);
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rc->mapping_offset = cpu_to_le32(sizeof(*rc));
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/* Table 13 Memory access properties */
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/* CCA: Cache Coherent Attribute */
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build_append_int_noprefix(table_data, 1 /* fully coherent */, 4);
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build_append_int_noprefix(table_data, 0, 1); /* AH: Note Allocation Hints */
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build_append_int_noprefix(table_data, 0, 2); /* Reserved */
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/* MAF: Note Memory Access Flags */
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build_append_int_noprefix(table_data, 0x3 /* CCA = CPM = DCAS = 1 */, 1);
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/* fully coherent device */
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rc->memory_properties.cache_coherency = cpu_to_le32(1);
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rc->memory_properties.memory_flags = 0x3; /* CCA = CPM = DCAS = 1 */
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rc->pci_segment_number = 0; /* MCFG pci_segment */
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build_append_int_noprefix(table_data, 0, 4); /* ATS Attribute */
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/* MCFG pci_segment */
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build_append_int_noprefix(table_data, 0, 4); /* PCI Segment number */
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/* Output Reference */
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if (vms->iommu == VIRT_IOMMU_SMMUV3) {
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AcpiIortIdMapping *range;
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/* translated RIDs connect to SMMUv3 node: RC -> SMMUv3 -> ITS */
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for (i = 0; i < smmu_idmaps->len; i++) {
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idmap = &rc->id_mapping_array[i];
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range = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i);
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idmap->input_base = cpu_to_le32(range->input_base);
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idmap->id_count = cpu_to_le32(range->id_count);
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idmap->output_base = cpu_to_le32(range->input_base);
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/* output IORT node is the smmuv3 node */
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idmap->output_reference = cpu_to_le32(smmu_offset);
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build_iort_id_mapping(table_data, range->input_base,
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range->id_count, smmu_offset);
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}
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/* bypassed RIDs connect to ITS group node directly: RC -> ITS */
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for (i = 0; i < its_idmaps->len; i++) {
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idmap = &rc->id_mapping_array[smmu_idmaps->len + i];
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range = &g_array_index(its_idmaps, AcpiIortIdMapping, i);
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idmap->input_base = cpu_to_le32(range->input_base);
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idmap->id_count = cpu_to_le32(range->id_count);
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idmap->output_base = cpu_to_le32(range->input_base);
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/* output IORT node is the ITS group node (the first node) */
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idmap->output_reference = cpu_to_le32(iort_node_offset);
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build_iort_id_mapping(table_data, range->input_base,
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range->id_count, iort_node_offset);
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}
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} else {
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/* Identity RID mapping covering the whole input RID range */
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idmap = &rc->id_mapping_array[0];
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idmap->input_base = cpu_to_le32(0);
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idmap->id_count = cpu_to_le32(0xFFFF);
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idmap->output_base = cpu_to_le32(0);
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/* output IORT node is the ITS group node (the first node) */
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idmap->output_reference = cpu_to_le32(iort_node_offset);
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build_iort_id_mapping(table_data, 0, 0xFFFF, IORT_NODE_OFFSET);
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}
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acpi_table_end(linker, &table);
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@ -188,75 +188,4 @@ struct AcpiGenericTimerTable {
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} QEMU_PACKED;
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typedef struct AcpiGenericTimerTable AcpiGenericTimerTable;
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/*
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* IORT node types
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*/
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#define ACPI_IORT_NODE_HEADER_DEF /* Node format common fields */ \
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uint8_t type; \
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uint16_t length; \
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uint8_t revision; \
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uint32_t reserved; \
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uint32_t mapping_count; \
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uint32_t mapping_offset;
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/* Values for node Type above */
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enum {
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ACPI_IORT_NODE_ITS_GROUP = 0x00,
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ACPI_IORT_NODE_NAMED_COMPONENT = 0x01,
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ACPI_IORT_NODE_PCI_ROOT_COMPLEX = 0x02,
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ACPI_IORT_NODE_SMMU = 0x03,
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ACPI_IORT_NODE_SMMU_V3 = 0x04
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};
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struct AcpiIortIdMapping {
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uint32_t input_base;
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uint32_t id_count;
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uint32_t output_base;
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uint32_t output_reference;
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uint32_t flags;
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} QEMU_PACKED;
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typedef struct AcpiIortIdMapping AcpiIortIdMapping;
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struct AcpiIortMemoryAccess {
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uint32_t cache_coherency;
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uint8_t hints;
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uint16_t reserved;
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uint8_t memory_flags;
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} QEMU_PACKED;
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typedef struct AcpiIortMemoryAccess AcpiIortMemoryAccess;
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struct AcpiIortItsGroup {
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ACPI_IORT_NODE_HEADER_DEF
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uint32_t its_count;
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uint32_t identifiers[];
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} QEMU_PACKED;
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typedef struct AcpiIortItsGroup AcpiIortItsGroup;
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#define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE 1
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struct AcpiIortSmmu3 {
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ACPI_IORT_NODE_HEADER_DEF
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uint64_t base_address;
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uint32_t flags;
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uint32_t reserved2;
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uint64_t vatos_address;
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uint32_t model;
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uint32_t event_gsiv;
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uint32_t pri_gsiv;
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uint32_t gerr_gsiv;
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uint32_t sync_gsiv;
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AcpiIortIdMapping id_mapping_array[];
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} QEMU_PACKED;
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typedef struct AcpiIortSmmu3 AcpiIortSmmu3;
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struct AcpiIortRC {
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ACPI_IORT_NODE_HEADER_DEF
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AcpiIortMemoryAccess memory_properties;
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uint32_t ats_attribute;
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uint32_t pci_segment_number;
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AcpiIortIdMapping id_mapping_array[];
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} QEMU_PACKED;
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typedef struct AcpiIortRC AcpiIortRC;
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#endif
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