mirror of https://github.com/proxmox/mirror_qemu
target-i386: introduce gen_prepare_cc
This makes the i386 front-end able to create CCPrepare structs for all condition, not just those that come from a single flag. In particular, JCC_L and JCC_LE can be optimized because gen_prepare_cc is not forced to return a result in bit 0 (unlike gen_setcc_slow). However, for now the slow jcc operations will still go through CC computation in a single-bit temporary, followed by a brcond if the temporary is nonzero. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>master
parent
bec93d7283
commit
276e6b5f06
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@ -1042,14 +1042,6 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg)
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#define gen_compute_eflags_c(s, reg, inv) \
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gen_do_setcc(reg, gen_prepare_eflags_c(s, reg), inv)
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#define gen_compute_eflags_p(s, reg) \
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gen_do_setcc(reg, gen_prepare_eflags_p(s, reg), false)
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#define gen_compute_eflags_s(s, reg, inv) \
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gen_do_setcc(reg, gen_prepare_eflags_s(s, reg), inv)
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#define gen_compute_eflags_o(s, reg) \
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gen_do_setcc(reg, gen_prepare_eflags_o(s, reg), false)
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#define gen_compute_eflags_z(s, reg, inv) \
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gen_do_setcc(reg, gen_prepare_eflags_z(s, reg), inv)
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static void gen_do_setcc(TCGv reg, struct CCPrepare cc, bool inv)
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{
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@ -1074,6 +1066,7 @@ static void gen_do_setcc(TCGv reg, struct CCPrepare cc, bool inv)
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}
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if (cc.mask != -1) {
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tcg_gen_andi_tl(reg, cc.reg, cc.mask);
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cc.reg = reg;
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}
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if (cc.use_reg2) {
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tcg_gen_setcond_tl(cc.cond, reg, cc.reg, cc.reg2);
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@ -1082,58 +1075,50 @@ static void gen_do_setcc(TCGv reg, struct CCPrepare cc, bool inv)
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}
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}
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static void gen_setcc_slow(DisasContext *s, int jcc_op, TCGv reg, bool inv)
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static CCPrepare gen_prepare_cc_slow(DisasContext *s, int jcc_op, TCGv reg)
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{
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switch(jcc_op) {
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case JCC_O:
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gen_compute_eflags_o(s, reg);
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break;
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return gen_prepare_eflags_o(s, reg);
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case JCC_B:
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gen_compute_eflags_c(s, reg, inv);
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inv = false;
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break;
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return gen_prepare_eflags_c(s, reg);
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case JCC_Z:
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gen_compute_eflags_z(s, reg, inv);
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inv = false;
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break;
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return gen_prepare_eflags_z(s, reg);
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case JCC_BE:
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gen_compute_eflags(s);
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tcg_gen_andi_tl(reg, cpu_cc_src, CC_Z | CC_C);
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tcg_gen_setcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, reg, reg, 0);
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return;
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return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src,
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.mask = CC_Z | CC_C };
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case JCC_S:
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gen_compute_eflags_s(s, reg, inv);
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inv = false;
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break;
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return gen_prepare_eflags_s(s, reg);
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case JCC_P:
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gen_compute_eflags_p(s, reg);
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break;
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return gen_prepare_eflags_p(s, reg);
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case JCC_L:
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gen_compute_eflags(s);
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tcg_gen_shri_tl(cpu_tmp0, cpu_cc_src, 11); /* CC_O */
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tcg_gen_shri_tl(reg, cpu_cc_src, 7); /* CC_S */
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tcg_gen_xor_tl(reg, reg, cpu_tmp0);
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tcg_gen_andi_tl(reg, reg, 1);
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break;
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if (TCGV_EQUAL(reg, cpu_cc_src)) {
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reg = cpu_tmp0;
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}
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tcg_gen_shri_tl(reg, cpu_cc_src, 4); /* CC_O -> CC_S */
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tcg_gen_xor_tl(reg, reg, cpu_cc_src);
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return (CCPrepare) { .cond = TCG_COND_NE, .reg = reg, .mask = CC_S };
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default:
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case JCC_LE:
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gen_compute_eflags(s);
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tcg_gen_shri_tl(cpu_tmp0, cpu_cc_src, 4); /* CC_O -> CC_S */
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tcg_gen_xor_tl(reg, cpu_tmp0, cpu_cc_src);
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tcg_gen_andi_tl(reg, reg, CC_S | CC_Z);
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tcg_gen_setcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, reg, reg, 0);
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break;
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}
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if (inv) {
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tcg_gen_xori_tl(reg, reg, 1);
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if (TCGV_EQUAL(reg, cpu_cc_src)) {
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reg = cpu_tmp0;
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}
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tcg_gen_shri_tl(reg, cpu_cc_src, 4); /* CC_O -> CC_S */
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tcg_gen_xor_tl(reg, reg, cpu_cc_src);
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return (CCPrepare) { .cond = TCG_COND_NE, .reg = reg,
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.mask = CC_S | CC_Z };
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}
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}
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/* perform a conditional store into register 'reg' according to jump opcode
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value 'b'. In the fast case, T0 is guaranted not to be used. */
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static inline void gen_setcc1(DisasContext *s, int b, TCGv reg)
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static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
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{
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int inv, jcc_op, size, cond;
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CCPrepare cc;
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TCGv t0;
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inv = b & 1;
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@ -1148,23 +1133,24 @@ static inline void gen_setcc1(DisasContext *s, int b, TCGv reg)
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size = s->cc_op - CC_OP_SUBB;
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switch (jcc_op) {
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case JCC_BE:
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cond = inv ? TCG_COND_GTU : TCG_COND_LEU;
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tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
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gen_extu(size, cpu_tmp4);
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t0 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false);
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tcg_gen_setcond_tl(cond, reg, cpu_tmp4, t0);
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cc = (CCPrepare) { .cond = TCG_COND_LEU, .reg = cpu_tmp4,
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.reg2 = t0, .mask = -1, .use_reg2 = true };
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break;
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case JCC_L:
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cond = inv ? TCG_COND_GE : TCG_COND_LT;
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cond = TCG_COND_LT;
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goto fast_jcc_l;
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case JCC_LE:
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cond = inv ? TCG_COND_GT : TCG_COND_LE;
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cond = TCG_COND_LE;
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fast_jcc_l:
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tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
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gen_exts(size, cpu_tmp4);
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t0 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, true);
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tcg_gen_setcond_tl(cond, reg, cpu_tmp4, t0);
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cc = (CCPrepare) { .cond = cond, .reg = cpu_tmp4,
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.reg2 = t0, .mask = -1, .use_reg2 = true };
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break;
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default:
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@ -1174,12 +1160,20 @@ static inline void gen_setcc1(DisasContext *s, int b, TCGv reg)
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default:
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slow_jcc:
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/* gen_setcc_slow actually generates good code for JC, JZ and JS */
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gen_setcc_slow(s, jcc_op, reg, inv);
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/* gen_prepare_cc_slow actually generates good code for JC, JZ and JS */
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cc = gen_prepare_cc_slow(s, jcc_op, reg);
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break;
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}
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if (inv) {
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cc.cond = tcg_invert_cond(cc.cond);
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}
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return cc;
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}
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#define gen_setcc1(s, b, reg) \
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gen_do_setcc(reg, gen_prepare_cc(s, b, reg), false)
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/* generate a conditional jump to label 'l1' according to jump opcode
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value 'b'. In the fast case, T0 is guaranted not to be used. */
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static inline void gen_jcc1(DisasContext *s, int b, int l1)
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@ -1292,9 +1286,8 @@ static inline void gen_jcc1(DisasContext *s, int b, int l1)
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break;
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default:
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slow_jcc:
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gen_setcc_slow(s, jcc_op, cpu_T[0], false);
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tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE,
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cpu_T[0], 0, l1);
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gen_setcc1(s, b, cpu_T[0]);
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tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[0], 0, l1);
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break;
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}
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}
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