mirror of https://github.com/proxmox/mirror_qemu
hw/pci-bridge/cxl-upstream: Add serial number extended capability support
Will be needed so there is a defined serial number for information queries via the Switch CCI. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230913133615.29876-1-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>master
parent
e967413fe0
commit
2c9ec2a827
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@ -14,14 +14,21 @@
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#include "hw/pci/msi.h"
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#include "hw/pci/msi.h"
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#include "hw/pci/pcie.h"
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#include "hw/pci/pcie.h"
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#include "hw/pci/pcie_port.h"
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#include "hw/pci/pcie_port.h"
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/*
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* Null value of all Fs suggested by IEEE RA guidelines for use of
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* EU, OUI and CID
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*/
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#define UI64_NULL (~0ULL)
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#define CXL_UPSTREAM_PORT_MSI_NR_VECTOR 2
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#define CXL_UPSTREAM_PORT_MSI_NR_VECTOR 2
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#define CXL_UPSTREAM_PORT_MSI_OFFSET 0x70
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#define CXL_UPSTREAM_PORT_MSI_OFFSET 0x70
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#define CXL_UPSTREAM_PORT_PCIE_CAP_OFFSET 0x90
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#define CXL_UPSTREAM_PORT_PCIE_CAP_OFFSET 0x90
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#define CXL_UPSTREAM_PORT_AER_OFFSET 0x100
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#define CXL_UPSTREAM_PORT_AER_OFFSET 0x100
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#define CXL_UPSTREAM_PORT_DVSEC_OFFSET \
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#define CXL_UPSTREAM_PORT_SN_OFFSET \
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(CXL_UPSTREAM_PORT_AER_OFFSET + PCI_ERR_SIZEOF)
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(CXL_UPSTREAM_PORT_AER_OFFSET + PCI_ERR_SIZEOF)
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#define CXL_UPSTREAM_PORT_DVSEC_OFFSET \
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(CXL_UPSTREAM_PORT_SN_OFFSET + PCI_EXT_CAP_DSN_SIZEOF)
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typedef struct CXLUpstreamPort {
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typedef struct CXLUpstreamPort {
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/*< private >*/
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/*< private >*/
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@ -30,6 +37,7 @@ typedef struct CXLUpstreamPort {
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/*< public >*/
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/*< public >*/
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CXLComponentState cxl_cstate;
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CXLComponentState cxl_cstate;
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DOECap doe_cdat;
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DOECap doe_cdat;
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uint64_t sn;
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} CXLUpstreamPort;
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} CXLUpstreamPort;
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CXLComponentState *cxl_usp_to_cstate(CXLUpstreamPort *usp)
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CXLComponentState *cxl_usp_to_cstate(CXLUpstreamPort *usp)
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@ -326,7 +334,9 @@ static void cxl_usp_realize(PCIDevice *d, Error **errp)
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if (rc) {
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if (rc) {
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goto err_cap;
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goto err_cap;
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}
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}
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if (usp->sn != UI64_NULL) {
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pcie_dev_ser_num_init(d, CXL_UPSTREAM_PORT_SN_OFFSET, usp->sn);
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}
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cxl_cstate->dvsec_offset = CXL_UPSTREAM_PORT_DVSEC_OFFSET;
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cxl_cstate->dvsec_offset = CXL_UPSTREAM_PORT_DVSEC_OFFSET;
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cxl_cstate->pdev = d;
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cxl_cstate->pdev = d;
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build_dvsecs(cxl_cstate);
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build_dvsecs(cxl_cstate);
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@ -366,6 +376,7 @@ static void cxl_usp_exitfn(PCIDevice *d)
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}
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}
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static Property cxl_upstream_props[] = {
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static Property cxl_upstream_props[] = {
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DEFINE_PROP_UINT64("sn", CXLUpstreamPort, sn, UI64_NULL),
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DEFINE_PROP_STRING("cdat", CXLUpstreamPort, cxl_cstate.cdat.filename),
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DEFINE_PROP_STRING("cdat", CXLUpstreamPort, cxl_cstate.cdat.filename),
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DEFINE_PROP_END_OF_LIST()
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DEFINE_PROP_END_OF_LIST()
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};
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};
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