mirror of https://github.com/proxmox/mirror_qemu
target/ppc: Disconnect hflags from MSR
Copying flags directly from msr has drawbacks: (1) msr bits mean different things per cpu, (2) msr has 64 bits on 64 cpus while tb->flags has only 32 bits. Create a enum to define these bits. Document the origin of each bit and validate those bits that must match MSR. This fixes the truncation of env->hflags to tb->flags, because we no longer have hflags bits set above bit 31. Most of the code in ppc_tr_init_disas_context is moved over to hreg_compute_hflags. Some of it is simple extractions from msr, some requires examining other cpu flags. Anything that is moved becomes a simple extract from hflags in ppc_tr_init_disas_context. Several existing bugs are left in ppc_tr_init_disas_context, where additional changes are required -- to be addressed in future patches. Remove a broken #if 0 block. Reported-by: Ivan Warren <ivan@vmfacility.fr> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210323184340.619757-3-richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>master
parent
edece45d4a
commit
2df4fe7abe
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@ -585,6 +585,31 @@ enum {
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POWERPC_FLAG_HID0_LE = 0x00400000,
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};
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/*
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* Bits for env->hflags.
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*
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* Most of these bits overlap with corresponding bits in MSR,
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* but some come from other sources. Those that do come from
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* the MSR are validated in hreg_compute_hflags.
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*/
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enum {
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HFLAGS_LE = 0, /* MSR_LE -- comes from elsewhere on 601 */
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HFLAGS_HV = 1, /* computed from MSR_HV and other state */
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HFLAGS_64 = 2, /* computed from MSR_CE and MSR_SF */
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HFLAGS_DR = 4, /* MSR_DR */
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HFLAGS_IR = 5, /* MSR_IR */
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HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */
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HFLAGS_VSX = 7, /* from MSR_VSX if cpu has VSX; avoid overlap w/ MSR_AP */
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HFLAGS_TM = 8, /* computed from MSR_TM */
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HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */
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HFLAGS_SE = 10, /* MSR_SE -- from elsewhere on embedded ppc */
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HFLAGS_FP = 13, /* MSR_FP */
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HFLAGS_PR = 14, /* MSR_PR */
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HFLAGS_SA = 22, /* MSR_SA */
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HFLAGS_AP = 23, /* MSR_AP */
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HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */
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};
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/*****************************************************************************/
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/* Floating point status and control register */
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#define FPSCR_DRN2 34 /* Decimal Floating-Point rounding control */
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@ -18,6 +18,7 @@
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "qemu/main-loop.h"
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#include "exec/exec-all.h"
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#include "sysemu/kvm.h"
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@ -87,24 +88,66 @@ void hreg_compute_mem_idx(CPUPPCState *env)
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void hreg_compute_hflags(CPUPPCState *env)
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{
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target_ulong hflags_mask;
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target_ulong msr = env->msr;
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uint32_t ppc_flags = env->flags;
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uint32_t hflags = 0;
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uint32_t msr_mask;
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/* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */
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hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) |
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(1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) |
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(1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR);
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hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB;
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hreg_compute_mem_idx(env);
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env->hflags = env->msr & hflags_mask;
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/* Some bits come straight across from MSR. */
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QEMU_BUILD_BUG_ON(MSR_LE != HFLAGS_LE);
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QEMU_BUILD_BUG_ON(MSR_PR != HFLAGS_PR);
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QEMU_BUILD_BUG_ON(MSR_DR != HFLAGS_DR);
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QEMU_BUILD_BUG_ON(MSR_IR != HFLAGS_IR);
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QEMU_BUILD_BUG_ON(MSR_FP != HFLAGS_FP);
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QEMU_BUILD_BUG_ON(MSR_SA != HFLAGS_SA);
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QEMU_BUILD_BUG_ON(MSR_AP != HFLAGS_AP);
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msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) |
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(1 << MSR_DR) | (1 << MSR_IR) |
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(1 << MSR_FP) | (1 << MSR_SA) | (1 << MSR_AP));
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if (env->flags & POWERPC_FLAG_HID0_LE) {
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if (ppc_flags & POWERPC_FLAG_HID0_LE) {
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/*
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* Note that MSR_LE is not set in env->msr_mask for this cpu,
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* and so will never be set in msr or hflags at this point.
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* and so will never be set in msr.
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*/
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uint32_t le = extract32(env->spr[SPR_HID0], 3, 1);
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env->hflags |= le << MSR_LE;
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hflags |= le << MSR_LE;
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}
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if (ppc_flags & POWERPC_FLAG_BE) {
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QEMU_BUILD_BUG_ON(MSR_BE != HFLAGS_BE);
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msr_mask |= 1 << MSR_BE;
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}
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if (ppc_flags & POWERPC_FLAG_SE) {
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QEMU_BUILD_BUG_ON(MSR_SE != HFLAGS_SE);
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msr_mask |= 1 << MSR_SE;
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}
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if (msr_is_64bit(env, msr)) {
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hflags |= 1 << HFLAGS_64;
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}
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if ((ppc_flags & POWERPC_FLAG_SPE) && (msr & (1 << MSR_SPE))) {
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hflags |= 1 << HFLAGS_SPE;
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}
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if (ppc_flags & POWERPC_FLAG_VRE) {
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QEMU_BUILD_BUG_ON(MSR_VR != HFLAGS_VR);
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msr_mask |= 1 << MSR_VR;
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}
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if ((ppc_flags & POWERPC_FLAG_VSX) && (msr & (1 << MSR_VSX))) {
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hflags |= 1 << HFLAGS_VSX;
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}
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if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) {
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hflags |= 1 << HFLAGS_TM;
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}
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#ifndef CONFIG_USER_ONLY
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if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) {
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hflags |= 1 << HFLAGS_HV;
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}
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#endif
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env->hflags = hflags | (msr & msr_mask);
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hreg_compute_mem_idx(env);
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}
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void cpu_interrupt_exittb(CPUState *cs)
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@ -7879,67 +7879,48 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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CPUPPCState *env = cs->env_ptr;
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uint32_t hflags = ctx->base.tb->flags;
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int bound;
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ctx->exception = POWERPC_EXCP_NONE;
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ctx->spr_cb = env->spr_cb;
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ctx->pr = msr_pr;
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ctx->pr = (hflags >> HFLAGS_PR) & 1;
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ctx->mem_idx = env->dmmu_idx;
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ctx->dr = msr_dr;
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#if !defined(CONFIG_USER_ONLY)
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ctx->hv = msr_hv || !env->has_hv_mode;
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#endif
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ctx->dr = (hflags >> HFLAGS_DR) & 1;
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ctx->hv = (hflags >> HFLAGS_HV) & 1;
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ctx->insns_flags = env->insns_flags;
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ctx->insns_flags2 = env->insns_flags2;
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ctx->access_type = -1;
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ctx->need_access_type = !mmu_is_64bit(env->mmu_model);
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ctx->le_mode = !!(env->hflags & (1 << MSR_LE));
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ctx->le_mode = (hflags >> HFLAGS_LE) & 1;
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ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE;
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ctx->flags = env->flags;
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#if defined(TARGET_PPC64)
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ctx->sf_mode = msr_is_64bit(env, env->msr);
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ctx->sf_mode = (hflags >> HFLAGS_64) & 1;
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ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
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#endif
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ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B
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|| env->mmu_model == POWERPC_MMU_601
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|| env->mmu_model & POWERPC_MMU_64;
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ctx->fpu_enabled = !!msr_fp;
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if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) {
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ctx->spe_enabled = !!msr_spe;
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} else {
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ctx->spe_enabled = false;
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}
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if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) {
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ctx->altivec_enabled = !!msr_vr;
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} else {
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ctx->altivec_enabled = false;
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}
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if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
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ctx->vsx_enabled = !!msr_vsx;
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} else {
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ctx->vsx_enabled = false;
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}
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ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1;
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ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1;
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ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1;
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ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1;
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if ((env->flags & POWERPC_FLAG_SCV)
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&& (env->spr[SPR_FSCR] & (1ull << FSCR_SCV))) {
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ctx->scv_enabled = true;
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} else {
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ctx->scv_enabled = false;
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}
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#if defined(TARGET_PPC64)
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if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
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ctx->tm_enabled = !!msr_tm;
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} else {
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ctx->tm_enabled = false;
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}
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#endif
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ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1;
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ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE);
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if ((env->flags & POWERPC_FLAG_SE) && msr_se) {
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ctx->singlestep_enabled = CPU_SINGLE_STEP;
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} else {
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ctx->singlestep_enabled = 0;
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ctx->singlestep_enabled = 0;
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if ((hflags >> HFLAGS_SE) & 1) {
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ctx->singlestep_enabled |= CPU_SINGLE_STEP;
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}
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if ((env->flags & POWERPC_FLAG_BE) && msr_be) {
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if ((hflags >> HFLAGS_BE) & 1) {
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ctx->singlestep_enabled |= CPU_BRANCH_STEP;
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}
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if ((env->flags & POWERPC_FLAG_DE) && msr_de) {
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@ -7956,10 +7937,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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if (unlikely(ctx->base.singlestep_enabled)) {
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ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP;
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}
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#if defined(DO_SINGLE_STEP) && 0
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/* Single step trace mode */
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msr_se = 1;
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#endif
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bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
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ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
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