mirror of https://github.com/proxmox/mirror_qemu
s390x/mmu: Inject PGM_ADDRESSING on bogus table addresses
Let's document how it works and inject PGM_ADDRESSING if reading of table entries fails. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>master
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81d7e3bc45
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2ed0cd7cd7
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@ -93,6 +93,27 @@ target_ulong mmu_real2abs(CPUS390XState *env, target_ulong raddr)
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return raddr;
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return raddr;
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}
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}
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static inline bool read_table_entry(CPUS390XState *env, hwaddr gaddr,
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uint64_t *entry)
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{
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CPUState *cs = env_cpu(env);
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/*
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* According to the PoP, these table addresses are "unpredictably real
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* or absolute". Also, "it is unpredictable whether the address wraps
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* or an addressing exception is recognized".
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*
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* We treat them as absolute addresses and don't wrap them.
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*/
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if (unlikely(address_space_read(cs->as, gaddr, MEMTXATTRS_UNSPECIFIED,
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(uint8_t *)entry, sizeof(*entry)) !=
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MEMTX_OK)) {
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return false;
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}
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*entry = be64_to_cpu(*entry);
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return true;
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}
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/* Decode page table entry (normal 4KB page) */
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/* Decode page table entry (normal 4KB page) */
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static int mmu_translate_pte(CPUS390XState *env, target_ulong vaddr,
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static int mmu_translate_pte(CPUS390XState *env, target_ulong vaddr,
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uint64_t asc, uint64_t pt_entry,
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uint64_t asc, uint64_t pt_entry,
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@ -118,7 +139,6 @@ static int mmu_translate_segment(CPUS390XState *env, target_ulong vaddr,
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target_ulong *raddr, int *flags, int rw,
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target_ulong *raddr, int *flags, int rw,
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bool exc)
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bool exc)
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{
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{
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CPUState *cs = env_cpu(env);
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uint64_t origin, offs, pt_entry;
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uint64_t origin, offs, pt_entry;
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if (st_entry & SEGMENT_ENTRY_RO) {
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if (st_entry & SEGMENT_ENTRY_RO) {
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@ -134,7 +154,9 @@ static int mmu_translate_segment(CPUS390XState *env, target_ulong vaddr,
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/* Look up 4KB page entry */
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/* Look up 4KB page entry */
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origin = st_entry & SEGMENT_ENTRY_ORIGIN;
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origin = st_entry & SEGMENT_ENTRY_ORIGIN;
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offs = (vaddr & VADDR_PX) >> 9;
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offs = (vaddr & VADDR_PX) >> 9;
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pt_entry = ldq_phys(cs->as, origin + offs);
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if (!read_table_entry(env, origin + offs, &pt_entry)) {
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return PGM_ADDRESSING;
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}
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return mmu_translate_pte(env, vaddr, asc, pt_entry, raddr, flags, rw, exc);
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return mmu_translate_pte(env, vaddr, asc, pt_entry, raddr, flags, rw, exc);
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}
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}
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@ -144,7 +166,6 @@ static int mmu_translate_region(CPUS390XState *env, target_ulong vaddr,
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target_ulong *raddr, int *flags, int rw,
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target_ulong *raddr, int *flags, int rw,
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bool exc)
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bool exc)
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{
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{
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CPUState *cs = env_cpu(env);
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uint64_t origin, offs, new_entry;
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uint64_t origin, offs, new_entry;
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const int pchks[4] = {
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const int pchks[4] = {
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PGM_SEGMENT_TRANS, PGM_REG_THIRD_TRANS,
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PGM_SEGMENT_TRANS, PGM_REG_THIRD_TRANS,
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@ -154,7 +175,9 @@ static int mmu_translate_region(CPUS390XState *env, target_ulong vaddr,
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origin = entry & REGION_ENTRY_ORIGIN;
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origin = entry & REGION_ENTRY_ORIGIN;
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offs = (vaddr >> (17 + 11 * level / 4)) & 0x3ff8;
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offs = (vaddr >> (17 + 11 * level / 4)) & 0x3ff8;
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new_entry = ldq_phys(cs->as, origin + offs);
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if (!read_table_entry(env, origin + offs, &new_entry)) {
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return PGM_ADDRESSING;
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}
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if ((new_entry & REGION_ENTRY_INV) != 0) {
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if ((new_entry & REGION_ENTRY_INV) != 0) {
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return pchks[level / 4];
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return pchks[level / 4];
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