mirror of https://github.com/proxmox/mirror_qemu
ppc: Move VSX ops out of translate.c
Makes things a bit more manageable Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>master
parent
0304af897b
commit
3014427af5
File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,721 @@
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/*** VSX extension ***/
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static inline TCGv_i64 cpu_vsrh(int n)
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{
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if (n < 32) {
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return cpu_fpr[n];
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} else {
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return cpu_avrh[n-32];
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}
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}
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static inline TCGv_i64 cpu_vsrl(int n)
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{
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if (n < 32) {
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return cpu_vsr[n];
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} else {
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return cpu_avrl[n-32];
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}
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}
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#define VSX_LOAD_SCALAR(name, operation) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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TCGv EA; \
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if (unlikely(!ctx->vsx_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_VSXU); \
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return; \
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} \
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gen_set_access_type(ctx, ACCESS_INT); \
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EA = tcg_temp_new(); \
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gen_addr_reg_index(ctx, EA); \
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gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
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/* NOTE: cpu_vsrl is undefined */ \
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tcg_temp_free(EA); \
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}
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VSX_LOAD_SCALAR(lxsdx, ld64)
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VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
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VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
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VSX_LOAD_SCALAR(lxsspx, ld32fs)
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static void gen_lxvd2x(DisasContext *ctx)
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{
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TCGv EA;
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if (unlikely(!ctx->vsx_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_VSXU);
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return;
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}
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gen_set_access_type(ctx, ACCESS_INT);
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EA = tcg_temp_new();
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gen_addr_reg_index(ctx, EA);
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gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
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tcg_gen_addi_tl(EA, EA, 8);
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gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
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tcg_temp_free(EA);
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}
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static void gen_lxvdsx(DisasContext *ctx)
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{
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TCGv EA;
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if (unlikely(!ctx->vsx_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_VSXU);
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return;
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}
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gen_set_access_type(ctx, ACCESS_INT);
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EA = tcg_temp_new();
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gen_addr_reg_index(ctx, EA);
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gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
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tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
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tcg_temp_free(EA);
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}
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static void gen_lxvw4x(DisasContext *ctx)
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{
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TCGv EA;
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TCGv_i64 tmp;
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TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
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TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
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if (unlikely(!ctx->vsx_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_VSXU);
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return;
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}
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gen_set_access_type(ctx, ACCESS_INT);
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EA = tcg_temp_new();
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tmp = tcg_temp_new_i64();
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gen_addr_reg_index(ctx, EA);
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gen_qemu_ld32u_i64(ctx, tmp, EA);
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tcg_gen_addi_tl(EA, EA, 4);
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gen_qemu_ld32u_i64(ctx, xth, EA);
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tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
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tcg_gen_addi_tl(EA, EA, 4);
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gen_qemu_ld32u_i64(ctx, tmp, EA);
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tcg_gen_addi_tl(EA, EA, 4);
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gen_qemu_ld32u_i64(ctx, xtl, EA);
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tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
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tcg_temp_free(EA);
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tcg_temp_free_i64(tmp);
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}
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#define VSX_STORE_SCALAR(name, operation) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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TCGv EA; \
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if (unlikely(!ctx->vsx_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_VSXU); \
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return; \
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} \
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gen_set_access_type(ctx, ACCESS_INT); \
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EA = tcg_temp_new(); \
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gen_addr_reg_index(ctx, EA); \
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gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
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tcg_temp_free(EA); \
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}
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VSX_STORE_SCALAR(stxsdx, st64)
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VSX_STORE_SCALAR(stxsiwx, st32_i64)
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VSX_STORE_SCALAR(stxsspx, st32fs)
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static void gen_stxvd2x(DisasContext *ctx)
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{
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TCGv EA;
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if (unlikely(!ctx->vsx_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_VSXU);
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return;
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}
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gen_set_access_type(ctx, ACCESS_INT);
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EA = tcg_temp_new();
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gen_addr_reg_index(ctx, EA);
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gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
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tcg_gen_addi_tl(EA, EA, 8);
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gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
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tcg_temp_free(EA);
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}
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static void gen_stxvw4x(DisasContext *ctx)
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{
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TCGv_i64 tmp;
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TCGv EA;
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if (unlikely(!ctx->vsx_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_VSXU);
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return;
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}
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gen_set_access_type(ctx, ACCESS_INT);
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EA = tcg_temp_new();
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gen_addr_reg_index(ctx, EA);
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tmp = tcg_temp_new_i64();
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tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
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gen_qemu_st32_i64(ctx, tmp, EA);
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tcg_gen_addi_tl(EA, EA, 4);
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gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
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tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
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tcg_gen_addi_tl(EA, EA, 4);
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gen_qemu_st32_i64(ctx, tmp, EA);
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tcg_gen_addi_tl(EA, EA, 4);
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gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
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tcg_temp_free(EA);
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tcg_temp_free_i64(tmp);
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}
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#define MV_VSRW(name, tcgop1, tcgop2, target, source) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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if (xS(ctx->opcode) < 32) { \
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if (unlikely(!ctx->fpu_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_FPU); \
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return; \
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} \
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} else { \
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if (unlikely(!ctx->altivec_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_VPU); \
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return; \
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} \
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} \
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TCGv_i64 tmp = tcg_temp_new_i64(); \
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tcg_gen_##tcgop1(tmp, source); \
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tcg_gen_##tcgop2(target, tmp); \
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tcg_temp_free_i64(tmp); \
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}
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MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
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cpu_vsrh(xS(ctx->opcode)))
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MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
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cpu_gpr[rA(ctx->opcode)])
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MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
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cpu_gpr[rA(ctx->opcode)])
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#if defined(TARGET_PPC64)
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#define MV_VSRD(name, target, source) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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if (xS(ctx->opcode) < 32) { \
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if (unlikely(!ctx->fpu_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_FPU); \
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return; \
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} \
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} else { \
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if (unlikely(!ctx->altivec_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_VPU); \
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return; \
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} \
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} \
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tcg_gen_mov_i64(target, source); \
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}
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MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
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MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
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#endif
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static void gen_xxpermdi(DisasContext *ctx)
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{
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if (unlikely(!ctx->vsx_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_VSXU);
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return;
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}
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if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
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(xT(ctx->opcode) == xB(ctx->opcode)))) {
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TCGv_i64 xh, xl;
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xh = tcg_temp_new_i64();
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xl = tcg_temp_new_i64();
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if ((DM(ctx->opcode) & 2) == 0) {
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tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
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} else {
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tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
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}
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if ((DM(ctx->opcode) & 1) == 0) {
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tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
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} else {
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tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
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}
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tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
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tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
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tcg_temp_free_i64(xh);
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tcg_temp_free_i64(xl);
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} else {
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if ((DM(ctx->opcode) & 2) == 0) {
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tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
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} else {
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tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
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}
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if ((DM(ctx->opcode) & 1) == 0) {
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tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
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} else {
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tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
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}
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}
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}
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#define OP_ABS 1
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#define OP_NABS 2
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#define OP_NEG 3
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#define OP_CPSGN 4
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#define SGN_MASK_DP 0x8000000000000000ull
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#define SGN_MASK_SP 0x8000000080000000ull
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#define VSX_SCALAR_MOVE(name, op, sgn_mask) \
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static void glue(gen_, name)(DisasContext * ctx) \
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{ \
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TCGv_i64 xb, sgm; \
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if (unlikely(!ctx->vsx_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_VSXU); \
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return; \
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} \
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xb = tcg_temp_new_i64(); \
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sgm = tcg_temp_new_i64(); \
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tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
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tcg_gen_movi_i64(sgm, sgn_mask); \
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switch (op) { \
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case OP_ABS: { \
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tcg_gen_andc_i64(xb, xb, sgm); \
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break; \
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} \
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case OP_NABS: { \
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tcg_gen_or_i64(xb, xb, sgm); \
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break; \
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} \
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case OP_NEG: { \
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tcg_gen_xor_i64(xb, xb, sgm); \
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break; \
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} \
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case OP_CPSGN: { \
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TCGv_i64 xa = tcg_temp_new_i64(); \
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tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
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tcg_gen_and_i64(xa, xa, sgm); \
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tcg_gen_andc_i64(xb, xb, sgm); \
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tcg_gen_or_i64(xb, xb, xa); \
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tcg_temp_free_i64(xa); \
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break; \
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} \
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} \
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tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
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tcg_temp_free_i64(xb); \
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tcg_temp_free_i64(sgm); \
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}
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VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
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VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
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VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
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VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
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#define VSX_VECTOR_MOVE(name, op, sgn_mask) \
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static void glue(gen_, name)(DisasContext * ctx) \
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{ \
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TCGv_i64 xbh, xbl, sgm; \
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if (unlikely(!ctx->vsx_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_VSXU); \
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return; \
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} \
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xbh = tcg_temp_new_i64(); \
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xbl = tcg_temp_new_i64(); \
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sgm = tcg_temp_new_i64(); \
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tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
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tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
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tcg_gen_movi_i64(sgm, sgn_mask); \
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switch (op) { \
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case OP_ABS: { \
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tcg_gen_andc_i64(xbh, xbh, sgm); \
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tcg_gen_andc_i64(xbl, xbl, sgm); \
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break; \
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} \
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case OP_NABS: { \
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tcg_gen_or_i64(xbh, xbh, sgm); \
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tcg_gen_or_i64(xbl, xbl, sgm); \
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break; \
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} \
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case OP_NEG: { \
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tcg_gen_xor_i64(xbh, xbh, sgm); \
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tcg_gen_xor_i64(xbl, xbl, sgm); \
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break; \
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} \
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case OP_CPSGN: { \
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TCGv_i64 xah = tcg_temp_new_i64(); \
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TCGv_i64 xal = tcg_temp_new_i64(); \
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tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
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tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
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tcg_gen_and_i64(xah, xah, sgm); \
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tcg_gen_and_i64(xal, xal, sgm); \
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tcg_gen_andc_i64(xbh, xbh, sgm); \
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tcg_gen_andc_i64(xbl, xbl, sgm); \
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tcg_gen_or_i64(xbh, xbh, xah); \
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tcg_gen_or_i64(xbl, xbl, xal); \
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tcg_temp_free_i64(xah); \
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tcg_temp_free_i64(xal); \
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break; \
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} \
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} \
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tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
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tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
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tcg_temp_free_i64(xbh); \
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tcg_temp_free_i64(xbl); \
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tcg_temp_free_i64(sgm); \
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}
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VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
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VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
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VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
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VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
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VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
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VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
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VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
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VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
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#define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
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static void gen_##name(DisasContext * ctx) \
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{ \
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TCGv_i32 opc; \
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if (unlikely(!ctx->vsx_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_VSXU); \
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return; \
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} \
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/* NIP cannot be restored if the memory exception comes from an helper */ \
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gen_update_nip(ctx, ctx->nip - 4); \
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opc = tcg_const_i32(ctx->opcode); \
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gen_helper_##name(cpu_env, opc); \
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tcg_temp_free_i32(opc); \
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}
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#define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
|
||||
static void gen_##name(DisasContext * ctx) \
|
||||
{ \
|
||||
if (unlikely(!ctx->vsx_enabled)) { \
|
||||
gen_exception(ctx, POWERPC_EXCP_VSXU); \
|
||||
return; \
|
||||
} \
|
||||
/* NIP cannot be restored if the exception comes */ \
|
||||
/* from a helper. */ \
|
||||
gen_update_nip(ctx, ctx->nip - 4); \
|
||||
\
|
||||
gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
|
||||
cpu_vsrh(xB(ctx->opcode))); \
|
||||
}
|
||||
|
||||
GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
|
||||
GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
|
||||
GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
|
||||
|
||||
GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
|
||||
GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
|
||||
GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
|
||||
GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
|
||||
GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
|
||||
GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
|
||||
GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
|
||||
GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
|
||||
GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
|
||||
GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
|
||||
GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
|
||||
GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
|
||||
GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
|
||||
GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
|
||||
GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
|
||||
GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
|
||||
GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
|
||||
|
||||
GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
|
||||
|
||||
GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
|
||||
GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
|
||||
|
||||
#define VSX_LOGICAL(name, tcg_op) \
|
||||
static void glue(gen_, name)(DisasContext * ctx) \
|
||||
{ \
|
||||
if (unlikely(!ctx->vsx_enabled)) { \
|
||||
gen_exception(ctx, POWERPC_EXCP_VSXU); \
|
||||
return; \
|
||||
} \
|
||||
tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
|
||||
cpu_vsrh(xB(ctx->opcode))); \
|
||||
tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
|
||||
cpu_vsrl(xB(ctx->opcode))); \
|
||||
}
|
||||
|
||||
VSX_LOGICAL(xxland, tcg_gen_and_i64)
|
||||
VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
|
||||
VSX_LOGICAL(xxlor, tcg_gen_or_i64)
|
||||
VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
|
||||
VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
|
||||
VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
|
||||
VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
|
||||
VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
|
||||
|
||||
#define VSX_XXMRG(name, high) \
|
||||
static void glue(gen_, name)(DisasContext * ctx) \
|
||||
{ \
|
||||
TCGv_i64 a0, a1, b0, b1; \
|
||||
if (unlikely(!ctx->vsx_enabled)) { \
|
||||
gen_exception(ctx, POWERPC_EXCP_VSXU); \
|
||||
return; \
|
||||
} \
|
||||
a0 = tcg_temp_new_i64(); \
|
||||
a1 = tcg_temp_new_i64(); \
|
||||
b0 = tcg_temp_new_i64(); \
|
||||
b1 = tcg_temp_new_i64(); \
|
||||
if (high) { \
|
||||
tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
|
||||
tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
|
||||
tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
|
||||
tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
|
||||
} else { \
|
||||
tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
|
||||
tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
|
||||
tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
|
||||
tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
|
||||
} \
|
||||
tcg_gen_shri_i64(a0, a0, 32); \
|
||||
tcg_gen_shri_i64(b0, b0, 32); \
|
||||
tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
|
||||
b0, a0, 32, 32); \
|
||||
tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
|
||||
b1, a1, 32, 32); \
|
||||
tcg_temp_free_i64(a0); \
|
||||
tcg_temp_free_i64(a1); \
|
||||
tcg_temp_free_i64(b0); \
|
||||
tcg_temp_free_i64(b1); \
|
||||
}
|
||||
|
||||
VSX_XXMRG(xxmrghw, 1)
|
||||
VSX_XXMRG(xxmrglw, 0)
|
||||
|
||||
static void gen_xxsel(DisasContext * ctx)
|
||||
{
|
||||
TCGv_i64 a, b, c;
|
||||
if (unlikely(!ctx->vsx_enabled)) {
|
||||
gen_exception(ctx, POWERPC_EXCP_VSXU);
|
||||
return;
|
||||
}
|
||||
a = tcg_temp_new_i64();
|
||||
b = tcg_temp_new_i64();
|
||||
c = tcg_temp_new_i64();
|
||||
|
||||
tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
|
||||
tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
|
||||
tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
|
||||
|
||||
tcg_gen_and_i64(b, b, c);
|
||||
tcg_gen_andc_i64(a, a, c);
|
||||
tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
|
||||
|
||||
tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
|
||||
tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
|
||||
tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
|
||||
|
||||
tcg_gen_and_i64(b, b, c);
|
||||
tcg_gen_andc_i64(a, a, c);
|
||||
tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
|
||||
|
||||
tcg_temp_free_i64(a);
|
||||
tcg_temp_free_i64(b);
|
||||
tcg_temp_free_i64(c);
|
||||
}
|
||||
|
||||
static void gen_xxspltw(DisasContext *ctx)
|
||||
{
|
||||
TCGv_i64 b, b2;
|
||||
TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
|
||||
cpu_vsrl(xB(ctx->opcode)) :
|
||||
cpu_vsrh(xB(ctx->opcode));
|
||||
|
||||
if (unlikely(!ctx->vsx_enabled)) {
|
||||
gen_exception(ctx, POWERPC_EXCP_VSXU);
|
||||
return;
|
||||
}
|
||||
|
||||
b = tcg_temp_new_i64();
|
||||
b2 = tcg_temp_new_i64();
|
||||
|
||||
if (UIM(ctx->opcode) & 1) {
|
||||
tcg_gen_ext32u_i64(b, vsr);
|
||||
} else {
|
||||
tcg_gen_shri_i64(b, vsr, 32);
|
||||
}
|
||||
|
||||
tcg_gen_shli_i64(b2, b, 32);
|
||||
tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
|
||||
tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
|
||||
|
||||
tcg_temp_free_i64(b);
|
||||
tcg_temp_free_i64(b2);
|
||||
}
|
||||
|
||||
static void gen_xxsldwi(DisasContext *ctx)
|
||||
{
|
||||
TCGv_i64 xth, xtl;
|
||||
if (unlikely(!ctx->vsx_enabled)) {
|
||||
gen_exception(ctx, POWERPC_EXCP_VSXU);
|
||||
return;
|
||||
}
|
||||
xth = tcg_temp_new_i64();
|
||||
xtl = tcg_temp_new_i64();
|
||||
|
||||
switch (SHW(ctx->opcode)) {
|
||||
case 0: {
|
||||
tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
|
||||
tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
|
||||
break;
|
||||
}
|
||||
case 1: {
|
||||
TCGv_i64 t0 = tcg_temp_new_i64();
|
||||
tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
|
||||
tcg_gen_shli_i64(xth, xth, 32);
|
||||
tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
|
||||
tcg_gen_shri_i64(t0, t0, 32);
|
||||
tcg_gen_or_i64(xth, xth, t0);
|
||||
tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
|
||||
tcg_gen_shli_i64(xtl, xtl, 32);
|
||||
tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
|
||||
tcg_gen_shri_i64(t0, t0, 32);
|
||||
tcg_gen_or_i64(xtl, xtl, t0);
|
||||
tcg_temp_free_i64(t0);
|
||||
break;
|
||||
}
|
||||
case 2: {
|
||||
tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
|
||||
tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
|
||||
break;
|
||||
}
|
||||
case 3: {
|
||||
TCGv_i64 t0 = tcg_temp_new_i64();
|
||||
tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
|
||||
tcg_gen_shli_i64(xth, xth, 32);
|
||||
tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
|
||||
tcg_gen_shri_i64(t0, t0, 32);
|
||||
tcg_gen_or_i64(xth, xth, t0);
|
||||
tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
|
||||
tcg_gen_shli_i64(xtl, xtl, 32);
|
||||
tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
|
||||
tcg_gen_shri_i64(t0, t0, 32);
|
||||
tcg_gen_or_i64(xtl, xtl, t0);
|
||||
tcg_temp_free_i64(t0);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
|
||||
tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
|
||||
|
||||
tcg_temp_free_i64(xth);
|
||||
tcg_temp_free_i64(xtl);
|
||||
}
|
||||
|
||||
#undef GEN_XX2FORM
|
||||
#undef GEN_XX3FORM
|
||||
#undef GEN_XX2IFORM
|
||||
#undef GEN_XX3_RC_FORM
|
||||
#undef GEN_XX3FORM_DM
|
||||
#undef VSX_LOGICAL
|
|
@ -0,0 +1,270 @@
|
|||
GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
|
||||
GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
|
||||
GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
|
||||
GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
|
||||
GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
|
||||
GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
|
||||
GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
|
||||
|
||||
GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
|
||||
GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
|
||||
GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
|
||||
GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
|
||||
GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
|
||||
|
||||
GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
|
||||
GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
|
||||
GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
|
||||
#if defined(TARGET_PPC64)
|
||||
GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
|
||||
GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
|
||||
#endif
|
||||
|
||||
#define GEN_XX2FORM(name, opc2, opc3, fl2) \
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
|
||||
|
||||
#define GEN_XX3FORM(name, opc2, opc3, fl2) \
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
|
||||
|
||||
#define GEN_XX2IFORM(name, opc2, opc3, fl2) \
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
|
||||
|
||||
#define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
|
||||
|
||||
#define GEN_XX3FORM_DM(name, opc2, opc3) \
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
|
||||
GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
|
||||
|
||||
GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
|
||||
GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
|
||||
GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
|
||||
GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
|
||||
|
||||
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
|
||||
GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
|
||||
GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
|
||||
GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
|
||||
GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
|
||||
GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
|
||||
GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
|
||||
GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
|
||||
|
||||
GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
|
||||
GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
|
||||
GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
|
||||
GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
|
||||
GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
|
||||
GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
|
||||
GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
|
||||
GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
|
||||
GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
|
||||
GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
|
||||
GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
|
||||
GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
|
||||
GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
|
||||
GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
|
||||
GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
|
||||
GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
|
||||
GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
|
||||
GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
|
||||
GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
|
||||
GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
|
||||
GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
|
||||
GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
|
||||
GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
|
||||
GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
|
||||
GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
|
||||
GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
|
||||
GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
|
||||
GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
|
||||
GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
|
||||
GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
|
||||
GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
|
||||
GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
|
||||
GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
|
||||
GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
|
||||
GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
|
||||
GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
|
||||
|
||||
GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
|
||||
GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
|
||||
GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
|
||||
GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
|
||||
GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
|
||||
GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
|
||||
GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
|
||||
GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
|
||||
GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
|
||||
GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
|
||||
GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
|
||||
GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
|
||||
GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
|
||||
GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
|
||||
GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
|
||||
GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
|
||||
GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
|
||||
GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
|
||||
|
||||
GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
|
||||
GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
|
||||
GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
|
||||
GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
|
||||
GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
|
||||
GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
|
||||
GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
|
||||
GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
|
||||
GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
|
||||
GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
|
||||
GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
|
||||
GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
|
||||
GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
|
||||
GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
|
||||
GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
|
||||
GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
|
||||
GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
|
||||
GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
|
||||
GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
|
||||
GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
|
||||
GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
|
||||
GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
|
||||
GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
|
||||
GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
|
||||
GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
|
||||
GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
|
||||
GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
|
||||
GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
|
||||
GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
|
||||
GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
|
||||
GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
|
||||
GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
|
||||
GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
|
||||
GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
|
||||
GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
|
||||
GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
|
||||
|
||||
GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
|
||||
GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
|
||||
GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
|
||||
GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
|
||||
GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
|
||||
GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
|
||||
GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
|
||||
GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
|
||||
GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
|
||||
GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
|
||||
GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
|
||||
GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
|
||||
GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
|
||||
GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
|
||||
GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
|
||||
GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
|
||||
GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
|
||||
GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
|
||||
GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
|
||||
GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
|
||||
GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
|
||||
GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
|
||||
GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
|
||||
GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
|
||||
GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
|
||||
GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
|
||||
GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
|
||||
GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
|
||||
GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
|
||||
GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
|
||||
GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
|
||||
GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
|
||||
GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
|
||||
GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
|
||||
GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
|
||||
GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
|
||||
|
||||
#define VSX_LOGICAL(name, opc2, opc3, fl2) \
|
||||
GEN_XX3FORM(name, opc2, opc3, fl2)
|
||||
|
||||
VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
|
||||
VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
|
||||
VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
|
||||
VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
|
||||
VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
|
||||
VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
|
||||
VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
|
||||
VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
|
||||
GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
|
||||
GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
|
||||
GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
|
||||
GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
|
||||
|
||||
#define GEN_XXSEL_ROW(opc3) \
|
||||
GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
|
||||
GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
|
||||
GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
|
||||
GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
|
||||
GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
|
||||
GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
|
||||
GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
|
||||
GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
|
||||
|
||||
GEN_XXSEL_ROW(0x00)
|
||||
GEN_XXSEL_ROW(0x01)
|
||||
GEN_XXSEL_ROW(0x02)
|
||||
GEN_XXSEL_ROW(0x03)
|
||||
GEN_XXSEL_ROW(0x04)
|
||||
GEN_XXSEL_ROW(0x05)
|
||||
GEN_XXSEL_ROW(0x06)
|
||||
GEN_XXSEL_ROW(0x07)
|
||||
GEN_XXSEL_ROW(0x08)
|
||||
GEN_XXSEL_ROW(0x09)
|
||||
GEN_XXSEL_ROW(0x0A)
|
||||
GEN_XXSEL_ROW(0x0B)
|
||||
GEN_XXSEL_ROW(0x0C)
|
||||
GEN_XXSEL_ROW(0x0D)
|
||||
GEN_XXSEL_ROW(0x0E)
|
||||
GEN_XXSEL_ROW(0x0F)
|
||||
GEN_XXSEL_ROW(0x10)
|
||||
GEN_XXSEL_ROW(0x11)
|
||||
GEN_XXSEL_ROW(0x12)
|
||||
GEN_XXSEL_ROW(0x13)
|
||||
GEN_XXSEL_ROW(0x14)
|
||||
GEN_XXSEL_ROW(0x15)
|
||||
GEN_XXSEL_ROW(0x16)
|
||||
GEN_XXSEL_ROW(0x17)
|
||||
GEN_XXSEL_ROW(0x18)
|
||||
GEN_XXSEL_ROW(0x19)
|
||||
GEN_XXSEL_ROW(0x1A)
|
||||
GEN_XXSEL_ROW(0x1B)
|
||||
GEN_XXSEL_ROW(0x1C)
|
||||
GEN_XXSEL_ROW(0x1D)
|
||||
GEN_XXSEL_ROW(0x1E)
|
||||
GEN_XXSEL_ROW(0x1F)
|
||||
|
||||
GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
|
Loading…
Reference in New Issue