mirror of https://github.com/proxmox/mirror_qemu
target/arm: Honor the HCR_EL2.TTLB bit
This bit traps EL1 access to tlb maintenance insns. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>master
Richard Henderson
Peter Maydell
parent
38262d8a73
commit
30881b7353
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@ -563,6 +563,16 @@ static CPAccessResult access_tacr(CPUARMState *env, const ARMCPRegInfo *ri,
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return CP_ACCESS_OK;
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}
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/* Check for traps from EL1 due to HCR_EL2.TTLB. */
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static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread)
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{
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if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TTLB)) {
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return CP_ACCESS_TRAP_EL2;
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}
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return CP_ACCESS_OK;
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}
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static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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{
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ARMCPU *cpu = env_archcpu(env);
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@ -2285,41 +2295,53 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
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.type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read },
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/* 32 bit ITLB invalidates */
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{ .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
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.writefn = tlbiall_write },
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{ .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
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.writefn = tlbimva_write },
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{ .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
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.writefn = tlbiasid_write },
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/* 32 bit DTLB invalidates */
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{ .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
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.writefn = tlbiall_write },
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{ .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
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.writefn = tlbimva_write },
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{ .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
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.writefn = tlbiasid_write },
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/* 32 bit TLB invalidates */
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{ .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
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.writefn = tlbiall_write },
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{ .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
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.writefn = tlbimva_write },
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{ .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
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.writefn = tlbiasid_write },
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{ .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
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.writefn = tlbimvaa_write },
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REGINFO_SENTINEL
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};
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static const ARMCPRegInfo v7mp_cp_reginfo[] = {
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/* 32 bit TLB invalidates, Inner Shareable */
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{ .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write },
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
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.writefn = tlbiall_is_write },
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{ .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
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.writefn = tlbimva_is_write },
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{ .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
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.type = ARM_CP_NO_RAW, .access = PL1_W,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
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.writefn = tlbiasid_is_write },
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{ .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
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.type = ARM_CP_NO_RAW, .access = PL1_W,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
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.writefn = tlbimvaa_is_write },
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REGINFO_SENTINEL
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};
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@ -4780,51 +4802,51 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
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/* TLBI operations */
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{ .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
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.access = PL1_W, .type = ARM_CP_NO_RAW,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_vmalle1is_write },
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{ .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
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.access = PL1_W, .type = ARM_CP_NO_RAW,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_vae1is_write },
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{ .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
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.access = PL1_W, .type = ARM_CP_NO_RAW,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_vmalle1is_write },
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{ .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
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.access = PL1_W, .type = ARM_CP_NO_RAW,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_vae1is_write },
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{ .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
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.access = PL1_W, .type = ARM_CP_NO_RAW,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_vae1is_write },
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{ .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
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.access = PL1_W, .type = ARM_CP_NO_RAW,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_vae1is_write },
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{ .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
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.access = PL1_W, .type = ARM_CP_NO_RAW,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_vmalle1_write },
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{ .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
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.access = PL1_W, .type = ARM_CP_NO_RAW,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_vae1_write },
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{ .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
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.access = PL1_W, .type = ARM_CP_NO_RAW,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_vmalle1_write },
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{ .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
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.access = PL1_W, .type = ARM_CP_NO_RAW,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_vae1_write },
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{ .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
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.access = PL1_W, .type = ARM_CP_NO_RAW,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_vae1_write },
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{ .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
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.access = PL1_W, .type = ARM_CP_NO_RAW,
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.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_vae1_write },
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{ .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
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@ -4910,14 +4932,17 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
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#endif
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/* TLB invalidate last level of translation table walk */
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{ .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
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.writefn = tlbimva_is_write },
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{ .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
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.type = ARM_CP_NO_RAW, .access = PL1_W,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
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.writefn = tlbimvaa_is_write },
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{ .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
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.writefn = tlbimva_write },
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{ .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
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.type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
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.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
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.writefn = tlbimvaa_write },
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{ .name = "TLBIMVALH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
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.type = ARM_CP_NO_RAW, .access = PL2_W,
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.writefn = tlbimva_hyp_write },
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