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target/riscv: Use env_cpu, env_archcpu 

Cleanup in the boilerplate that each target must define.
Replace riscv_env_get_cpu with env_archcpu.  The combination
CPU(riscv_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
master
Richard Henderson 2019-03-22 19:11:37 -07:00
parent db70b31144
commit 3109cd98a6
5 changed files with 14 additions and 22 deletions
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2
linux-user/riscv/cpu_loop.c
View File

@ -25,7 +25,7 @@
void cpu_loop(CPURISCVState *env)
{
CPUState *cs = CPU(riscv_env_get_cpu(env));
CPUState *cs = env_cpu(env);
int trapnr, signum, sigcode;
target_ulong sigaddr;
target_ulong ret;

5
target/riscv/cpu.h
View File

@ -221,11 +221,6 @@ typedef struct RISCVCPU {
} cfg;
} RISCVCPU;
static inline RISCVCPU *riscv_env_get_cpu(CPURISCVState *env)
{
return container_of(env, RISCVCPU, env);
}
static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
{
return (env->misa & ext) != 0;

10
target/riscv/cpu_helper.c
View File

@ -89,14 +89,12 @@ struct CpuAsyncInfo {
static void riscv_cpu_update_mip_irqs_async(CPUState *target_cpu_state,
run_on_cpu_data data)
{
CPURISCVState *env = &RISCV_CPU(target_cpu_state)->env;
RISCVCPU *cpu = riscv_env_get_cpu(env);
struct CpuAsyncInfo *info = (struct CpuAsyncInfo *) data.host_ptr;
if (info->new_mip) {
cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
cpu_interrupt(target_cpu_state, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
cpu_reset_interrupt(target_cpu_state, CPU_INTERRUPT_HARD);
}
g_free(info);
@ -212,7 +210,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
}
}
CPUState *cs = CPU(riscv_env_get_cpu(env));
CPUState *cs = env_cpu(env);
int va_bits = PGSHIFT + levels * ptidxbits;
target_ulong mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
target_ulong masked_msbs = (addr >> (va_bits - 1)) & mask;
@ -341,7 +339,7 @@ restart:
static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
MMUAccessType access_type)
{
CPUState *cs = CPU(riscv_env_get_cpu(env));
CPUState *cs = env_cpu(env);
int page_fault_exceptions =
(env->priv_ver >= PRIV_VERSION_1_10_0) &&
get_field(env->satp, SATP_MODE) != VM_1_10_MBARE;

12
target/riscv/csr.c
View File

@ -296,7 +296,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
if (env->priv_ver <= PRIV_VERSION_1_09_1) {
if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP |
MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) {
tlb_flush(CPU(riscv_env_get_cpu(env)));
tlb_flush(env_cpu(env));
}
mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
@ -307,7 +307,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
if (env->priv_ver >= PRIV_VERSION_1_10_0) {
if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
MSTATUS_MPRV | MSTATUS_SUM)) {
tlb_flush(CPU(riscv_env_get_cpu(env)));
tlb_flush(env_cpu(env));
}
mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
@ -382,7 +382,7 @@ static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
/* flush translation cache */
if (val != env->misa) {
tb_flush(CPU(riscv_env_get_cpu(env)));
tb_flush(env_cpu(env));
}
env->misa = val;
@ -549,7 +549,7 @@ static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val)
static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask)
{
RISCVCPU *cpu = riscv_env_get_cpu(env);
RISCVCPU *cpu = env_archcpu(env);
/* Allow software control of delegable interrupts not claimed by hardware */
target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
uint32_t old_mip;
@ -712,7 +712,7 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
if (env->priv_ver <= PRIV_VERSION_1_09_1 && (val ^ env->sptbr)) {
tlb_flush(CPU(riscv_env_get_cpu(env)));
tlb_flush(env_cpu(env));
env->sptbr = val & (((target_ulong)
1 << (TARGET_PHYS_ADDR_SPACE_BITS - PGSHIFT)) - 1);
}
@ -724,7 +724,7 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
return -1;
} else {
if((val ^ env->satp) & SATP_ASID) {
tlb_flush(CPU(riscv_env_get_cpu(env)));
tlb_flush(env_cpu(env));
}
env->satp = val;
}

7
target/riscv/op_helper.c
View File

@ -28,7 +28,7 @@
void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
uint32_t exception, uintptr_t pc)
{
CPUState *cs = CPU(riscv_env_get_cpu(env));
CPUState *cs = env_cpu(env);
qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception);
cs->exception_index = exception;
cpu_loop_exit_restore(cs, pc);
@ -128,7 +128,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
void helper_wfi(CPURISCVState *env)
{
CPUState *cs = CPU(riscv_env_get_cpu(env));
CPUState *cs = env_cpu(env);
if (env->priv == PRV_S &&
env->priv_ver >= PRIV_VERSION_1_10_0 &&
@ -143,8 +143,7 @@ void helper_wfi(CPURISCVState *env)
void helper_tlb_flush(CPURISCVState *env)
{
RISCVCPU *cpu = riscv_env_get_cpu(env);
CPUState *cs = CPU(cpu);
CPUState *cs = env_cpu(env);
if (!(env->priv >= PRV_S) ||
(env->priv == PRV_S &&
env->priv_ver >= PRIV_VERSION_1_10_0 &&