mirror of https://github.com/proxmox/mirror_qemu
target/arm: Move ID_AA64ISAR* test functions together
Move the feature test functions that test ID_AA64ISAR* fields together. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231024163510.2972081-5-peter.maydell@linaro.orgmaster
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5181c751af
commit
338ddfb1f3
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@ -451,6 +451,16 @@ static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id)
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return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0;
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}
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static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2;
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}
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static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0;
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}
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static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
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@ -514,16 +524,6 @@ static inline bool isar_feature_aa64_pauth_qarma3(const ARMISARegisters *id)
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return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3) != 0;
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}
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static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2;
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}
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static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0;
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}
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static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
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@ -554,6 +554,31 @@ static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id)
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return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0;
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}
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static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0;
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}
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static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2;
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}
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static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0;
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}
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static inline bool isar_feature_aa64_hbc(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, BC) != 0;
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}
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static inline bool isar_feature_aa64_mops(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, MOPS);
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}
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static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
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{
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/* We always set the AdvSIMD and FP fields identically. */
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@ -804,26 +829,6 @@ static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id)
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FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
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}
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static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0;
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}
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static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2;
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}
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static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0;
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}
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static inline bool isar_feature_aa64_hbc(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, BC) != 0;
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}
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static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
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@ -922,11 +927,6 @@ static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id)
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return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0;
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}
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static inline bool isar_feature_aa64_mops(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, MOPS);
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}
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/*
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* Feature tests for "does this exist in either 32-bit or 64-bit?"
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*/
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