mirror of https://github.com/proxmox/mirror_qemu
target/ppc: Implemented xvi*ger* instructions
Implement the following PowerISA v3.1 instructions: xvi4ger8: VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) xvi4ger8pp: VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) Positive multiply, Positive accumulate xvi8ger4: VSX Vector 4-bit Signed Integer GER (rank-8 update) xvi8ger4pp: VSX Vector 4-bit Signed Integer GER (rank-8 update) Positive multiply, Positive accumulate xvi8ger4spp: VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) with Saturate Positive multiply, Positive accumulate xvi16ger2: VSX Vector 16-bit Signed Integer GER (rank-2 update) xvi16ger2pp: VSX Vector 16-bit Signed Integer GER (rank-2 update) Positive multiply, Positive accumulate xvi16ger2s: VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation xvi16ger2spp: VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation Positive multiply, Positive accumulate Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220524140537.27451-3-lucas.araujo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>master
Lucas Mateus Castro (alqotel)
Daniel Henrique Barboza
parent
a702c5339e
commit
345531533f
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@ -238,6 +238,7 @@ typedef union _ppc_vsr_t {
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typedef ppc_vsr_t ppc_avr_t;
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typedef ppc_vsr_t ppc_fprp_t;
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typedef ppc_vsr_t ppc_acc_t;
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#if !defined(CONFIG_USER_ONLY)
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/* Software TLB cache */
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@ -133,6 +133,10 @@ DEF_HELPER_FLAGS_1(ftsqrt, TCG_CALL_NO_RWG_SE, i32, i64)
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#define dh_ctype_vsr ppc_vsr_t *
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#define dh_typecode_vsr dh_typecode_ptr
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#define dh_alias_acc ptr
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#define dh_ctype_acc ppc_acc_t *
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#define dh_typecode_acc dh_typecode_ptr
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DEF_HELPER_FLAGS_3(vavgub, TCG_CALL_NO_RWG, void, avr, avr, avr)
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DEF_HELPER_FLAGS_3(vavguh, TCG_CALL_NO_RWG, void, avr, avr, avr)
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DEF_HELPER_FLAGS_3(vavguw, TCG_CALL_NO_RWG, void, avr, avr, avr)
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@ -537,6 +541,15 @@ DEF_HELPER_FLAGS_5(XXBLENDVB, TCG_CALL_NO_RWG, void, vsr, vsr, vsr, vsr, i32)
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DEF_HELPER_FLAGS_5(XXBLENDVH, TCG_CALL_NO_RWG, void, vsr, vsr, vsr, vsr, i32)
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DEF_HELPER_FLAGS_5(XXBLENDVW, TCG_CALL_NO_RWG, void, vsr, vsr, vsr, vsr, i32)
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DEF_HELPER_FLAGS_5(XXBLENDVD, TCG_CALL_NO_RWG, void, vsr, vsr, vsr, vsr, i32)
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DEF_HELPER_5(XVI4GER8, void, env, vsr, vsr, acc, i32)
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DEF_HELPER_5(XVI4GER8PP, void, env, vsr, vsr, acc, i32)
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DEF_HELPER_5(XVI8GER4, void, env, vsr, vsr, acc, i32)
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DEF_HELPER_5(XVI8GER4PP, void, env, vsr, vsr, acc, i32)
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DEF_HELPER_5(XVI8GER4SPP, void, env, vsr, vsr, acc, i32)
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DEF_HELPER_5(XVI16GER2, void, env, vsr, vsr, acc, i32)
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DEF_HELPER_5(XVI16GER2S, void, env, vsr, vsr, acc, i32)
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DEF_HELPER_5(XVI16GER2PP, void, env, vsr, vsr, acc, i32)
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DEF_HELPER_5(XVI16GER2SPP, void, env, vsr, vsr, acc, i32)
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DEF_HELPER_2(efscfsi, i32, env, i32)
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DEF_HELPER_2(efscfui, i32, env, i32)
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@ -175,6 +175,12 @@
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&XX3 xt xa xb
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@XX3 ...... ..... ..... ..... ........ ... &XX3 xt=%xx_xt xa=%xx_xa xb=%xx_xb
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# 32 bit GER instructions have all mask bits considered 1
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&MMIRR_XX3 xa xb xt pmsk xmsk ymsk
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%xx_at 23:3
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@XX3_at ...... ... .. ..... ..... ........ ... &MMIRR_XX3 xt=%xx_at xb=%xx_xb \
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pmsk=255 xmsk=15 ymsk=15
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&XX3_dm xt xa xb dm
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@XX3_dm ...... ..... ..... ..... . dm:2 ..... ... &XX3_dm xt=%xx_xt xa=%xx_xa xb=%xx_xb
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@ -743,3 +749,15 @@ RFEBB 010011-------------- . 0010010010 - @XL_s
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XXMFACC 011111 ... -- 00000 ----- 0010110001 - @X_a
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XXMTACC 011111 ... -- 00001 ----- 0010110001 - @X_a
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XXSETACCZ 011111 ... -- 00011 ----- 0010110001 - @X_a
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## VSX GER instruction
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XVI4GER8 111011 ... -- ..... ..... 00100011 ..- @XX3_at xa=%xx_xa
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XVI4GER8PP 111011 ... -- ..... ..... 00100010 ..- @XX3_at xa=%xx_xa
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XVI8GER4 111011 ... -- ..... ..... 00000011 ..- @XX3_at xa=%xx_xa
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XVI8GER4PP 111011 ... -- ..... ..... 00000010 ..- @XX3_at xa=%xx_xa
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XVI16GER2 111011 ... -- ..... ..... 01001011 ..- @XX3_at xa=%xx_xa
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XVI16GER2PP 111011 ... -- ..... ..... 01101011 ..- @XX3_at xa=%xx_xa
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XVI8GER4SPP 111011 ... -- ..... ..... 01100011 ..- @XX3_at xa=%xx_xa
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XVI16GER2S 111011 ... -- ..... ..... 00101011 ..- @XX3_at xa=%xx_xa
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XVI16GER2SPP 111011 ... -- ..... ..... 00101010 ..- @XX3_at xa=%xx_xa
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@ -782,6 +782,136 @@ VCT(uxs, cvtsduw, u32)
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VCT(sxs, cvtsdsw, s32)
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#undef VCT
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typedef int64_t do_ger(uint32_t, uint32_t, uint32_t);
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static int64_t ger_rank8(uint32_t a, uint32_t b, uint32_t mask)
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{
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int64_t psum = 0;
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for (int i = 0; i < 8; i++, mask >>= 1) {
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if (mask & 1) {
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psum += sextract32(a, 4 * i, 4) * sextract32(b, 4 * i, 4);
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}
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}
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return psum;
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}
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static int64_t ger_rank4(uint32_t a, uint32_t b, uint32_t mask)
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{
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int64_t psum = 0;
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for (int i = 0; i < 4; i++, mask >>= 1) {
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if (mask & 1) {
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psum += sextract32(a, 8 * i, 8) * (int64_t)extract32(b, 8 * i, 8);
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}
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}
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return psum;
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}
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static int64_t ger_rank2(uint32_t a, uint32_t b, uint32_t mask)
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{
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int64_t psum = 0;
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for (int i = 0; i < 2; i++, mask >>= 1) {
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if (mask & 1) {
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psum += sextract32(a, 16 * i, 16) * sextract32(b, 16 * i, 16);
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}
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}
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return psum;
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}
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static void xviger(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, ppc_acc_t *at,
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uint32_t mask, bool sat, bool acc, do_ger ger)
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{
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uint8_t pmsk = FIELD_EX32(mask, GER_MSK, PMSK),
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xmsk = FIELD_EX32(mask, GER_MSK, XMSK),
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ymsk = FIELD_EX32(mask, GER_MSK, YMSK);
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uint8_t xmsk_bit, ymsk_bit;
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int64_t psum;
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int i, j;
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for (i = 0, xmsk_bit = 1 << 3; i < 4; i++, xmsk_bit >>= 1) {
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for (j = 0, ymsk_bit = 1 << 3; j < 4; j++, ymsk_bit >>= 1) {
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if ((xmsk_bit & xmsk) && (ymsk_bit & ymsk)) {
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psum = ger(a->VsrW(i), b->VsrW(j), pmsk);
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if (acc) {
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psum += at[i].VsrSW(j);
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}
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if (sat && psum > INT32_MAX) {
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set_vscr_sat(env);
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at[i].VsrSW(j) = INT32_MAX;
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} else if (sat && psum < INT32_MIN) {
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set_vscr_sat(env);
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at[i].VsrSW(j) = INT32_MIN;
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} else {
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at[i].VsrSW(j) = (int32_t) psum;
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}
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} else {
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at[i].VsrSW(j) = 0;
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}
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}
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}
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}
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QEMU_FLATTEN
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void helper_XVI4GER8(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
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ppc_acc_t *at, uint32_t mask)
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{
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xviger(env, a, b, at, mask, false, false, ger_rank8);
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}
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QEMU_FLATTEN
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void helper_XVI4GER8PP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
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ppc_acc_t *at, uint32_t mask)
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{
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xviger(env, a, b, at, mask, false, true, ger_rank8);
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}
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QEMU_FLATTEN
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void helper_XVI8GER4(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
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ppc_acc_t *at, uint32_t mask)
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{
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xviger(env, a, b, at, mask, false, false, ger_rank4);
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}
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QEMU_FLATTEN
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void helper_XVI8GER4PP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
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ppc_acc_t *at, uint32_t mask)
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{
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xviger(env, a, b, at, mask, false, true, ger_rank4);
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}
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QEMU_FLATTEN
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void helper_XVI8GER4SPP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
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ppc_acc_t *at, uint32_t mask)
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{
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xviger(env, a, b, at, mask, true, true, ger_rank4);
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}
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QEMU_FLATTEN
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void helper_XVI16GER2(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
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ppc_acc_t *at, uint32_t mask)
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{
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xviger(env, a, b, at, mask, false, false, ger_rank2);
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}
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QEMU_FLATTEN
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void helper_XVI16GER2S(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
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ppc_acc_t *at, uint32_t mask)
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{
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xviger(env, a, b, at, mask, true, false, ger_rank2);
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}
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QEMU_FLATTEN
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void helper_XVI16GER2PP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
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ppc_acc_t *at, uint32_t mask)
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{
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xviger(env, a, b, at, mask, false, true, ger_rank2);
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}
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QEMU_FLATTEN
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void helper_XVI16GER2SPP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
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ppc_acc_t *at, uint32_t mask)
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{
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xviger(env, a, b, at, mask, true, true, ger_rank2);
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}
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target_ulong helper_vclzlsbb(ppc_avr_t *r)
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{
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target_ulong count = 0;
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@ -18,6 +18,8 @@
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#ifndef PPC_INTERNAL_H
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#define PPC_INTERNAL_H
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#include "hw/registerfields.h"
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#define FUNC_MASK(name, ret_type, size, max_val) \
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static inline ret_type name(uint##size##_t start, \
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uint##size##_t end) \
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@ -291,4 +293,17 @@ G_NORETURN void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
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uintptr_t retaddr);
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#endif
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FIELD(GER_MSK, XMSK, 0, 4)
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FIELD(GER_MSK, YMSK, 4, 4)
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FIELD(GER_MSK, PMSK, 8, 8)
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static inline int ger_pack_masks(int pmsk, int ymsk, int xmsk)
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{
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int msk = 0;
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msk = FIELD_DP32(msk, GER_MSK, XMSK, xmsk);
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msk = FIELD_DP32(msk, GER_MSK, YMSK, ymsk);
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msk = FIELD_DP32(msk, GER_MSK, PMSK, pmsk);
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return msk;
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}
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#endif /* PPC_INTERNAL_H */
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@ -17,6 +17,13 @@ static inline TCGv_ptr gen_vsr_ptr(int reg)
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return r;
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}
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static inline TCGv_ptr gen_acc_ptr(int reg)
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{
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TCGv_ptr r = tcg_temp_new_ptr();
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tcg_gen_addi_ptr(r, cpu_env, acc_full_offset(reg));
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return r;
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}
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#define VSX_LOAD_SCALAR(name, operation) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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@ -2847,6 +2854,40 @@ static bool trans_XXSETACCZ(DisasContext *ctx, arg_X_a *a)
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return true;
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}
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static bool do_ger(DisasContext *ctx, arg_MMIRR_XX3 *a,
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void (*helper)(TCGv_env, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32))
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{
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uint32_t mask;
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TCGv_ptr xt, xa, xb;
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REQUIRE_INSNS_FLAGS2(ctx, ISA310);
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REQUIRE_VSX(ctx);
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if (unlikely((a->xa / 4 == a->xt) || (a->xb / 4 == a->xt))) {
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gen_invalid(ctx);
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return true;
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}
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xt = gen_acc_ptr(a->xt);
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xa = gen_vsr_ptr(a->xa);
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xb = gen_vsr_ptr(a->xb);
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mask = ger_pack_masks(a->pmsk, a->ymsk, a->xmsk);
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helper(cpu_env, xa, xb, xt, tcg_constant_i32(mask));
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tcg_temp_free_ptr(xt);
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tcg_temp_free_ptr(xa);
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tcg_temp_free_ptr(xb);
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return true;
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}
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TRANS(XVI4GER8, do_ger, gen_helper_XVI4GER8)
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TRANS(XVI4GER8PP, do_ger, gen_helper_XVI4GER8PP)
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TRANS(XVI8GER4, do_ger, gen_helper_XVI8GER4)
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TRANS(XVI8GER4PP, do_ger, gen_helper_XVI8GER4PP)
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TRANS(XVI8GER4SPP, do_ger, gen_helper_XVI8GER4SPP)
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TRANS(XVI16GER2, do_ger, gen_helper_XVI16GER2)
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TRANS(XVI16GER2PP, do_ger, gen_helper_XVI16GER2PP)
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TRANS(XVI16GER2S, do_ger, gen_helper_XVI16GER2S)
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TRANS(XVI16GER2SPP, do_ger, gen_helper_XVI16GER2SPP)
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#undef GEN_XX2FORM
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#undef GEN_XX3FORM
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#undef GEN_XX2IFORM
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