vitalif
/
mirror_qemu
mirror of https://github.com/proxmox/mirror_qemu
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

MIPS patches queue 

- Tidy up the GT64120 north bridge
 - Move XBurst Media eXtension Unit code to mxu_translate.c
 - Convert TX79 to decodetree
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmBNQFwACgkQ4+MsLN6t
 wN41IBAAq9Q08W0dEXXHoX9iNkBF5qjuXXUfXP++kv7yDYOrT9DUcFtM09Gr9rgu
 lOq2Bl0P3GMtiyC2pgYw7N6/0IBIBB0ddynaNy+Pcgd28naD+SMoEhKGOFWFHs7+
 +lEKv8Xsb2onbaDcXgHBIC46vvZbIvEXcdSXpfOSeohFUxgvKWLB7AcjT+yXNyls
 NvYo0fePBkc1qTbSVqcT+E9wOq2l7T9nvknIJuPQNL365oAIXnR7gJR6x1FC1k5S
 r5Rj244EwVHaUtzlc6f/RESGQpfL/8AioZm9SfAmxvLCLhXOQ1AaEcUVYooeb8b4
 gD3WSOyw9UnYKc77RqPrJLA9TO78UrkaEdT1M4Hys6HuZjmomt6y7uQPli2BQlp3
 S0FFlbCw7KgYUy4NCxTDDxKpgRSt4CkrTFpBWJQ2OW8LCCkWWOCrrtU5r0RPOFsf
 nFIdHD0i+VSXRiS2INCIvyPNdBkoud3JQVyXRV+IKQupDZPxN7x5vcEx/J9tScUf
 LKwgnJZvsfp1kQwqfRrBmw4vyqpYh9y6z89vAnuwIoHZMCsitrpRkejsq0v0EbRm
 iCRp3LO9msbEGTJI2pB+E+AgSJUndUYu5TZYAsddaGfgiS4eZN0aOyj7urLbvnsx
 28XgVQXOokfyZhs3Ca+8vFF0xioriOtGmAR/JacFxgeWTX7c2VU=
 =uGJE
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/philmd/tags/mips-20210313' into staging

MIPS patches queue

- Tidy up the GT64120 north bridge
- Move XBurst Media eXtension Unit code to mxu_translate.c
- Convert TX79 to decodetree

# gpg: Signature made Sat 13 Mar 2021 22:44:44 GMT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* remotes/philmd/tags/mips-20210313: (27 commits)
  target/mips/tx79: Salvage instructions description comment
  target/mips: Remove 'C790 Multimedia Instructions' dead code
  target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree
  target/mips/tx79: Move PCPYH opcode to decodetree
  target/mips/translate: Simplify PCPYH using deposit_i64()
  target/mips/translate: Make gen_rdhwr() public
  target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree
  target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree
  target/mips: Use gen_load_gpr[_hi]() when possible
  target/mips: Extract MXU code to new mxu_translate.c file
  target/mips: Introduce mxu_translate_init() helper
  target/mips: Simplify decode_opc_mxu() ifdef'ry
  target/mips: Convert decode_ase_mxu() to decodetree prototype
  target/mips: Rename decode_opc_mxu() as decode_ase_mxu()
  target/mips: Move MUL opcode check from decode_mxu() to decode_legacy()
  target/mips: Use OPC_MUL instead of OPC__MXU_MUL
  target/mips: Pass instruction opcode to decode_opc_mxu()
  target/mips: Remove unused CPUMIPSState* from MXU functions
  target/mips: Remove XBurst Media eXtension Unit dead code
  target/mips: Rewrite complex ifdef'ry
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
master
Peter Maydell 2021-03-14 19:16:11 +00:00
parent 6157b0e197 d27fadddc6
commit 36d840f35b
9 changed files with 2057 additions and 3672 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

59
hw/mips/gt64xxx_pci.c
View File

@ -385,13 +385,13 @@ static void gt64120_writel(void *opaque, hwaddr addr,
{
GT64120State *s = opaque;
PCIHostState *phb = PCI_HOST_BRIDGE(s);
uint32_t saddr;
uint32_t saddr = addr >> 2;
trace_gt64120_write(addr, val);
if (!(s->regs[GT_CPU] & 0x00001000)) {
val = bswap32(val);
}
saddr = (addr & 0xfff) >> 2;
switch (saddr) {
/* CPU Configuration */
@ -464,7 +464,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
/* Read-only registers, do nothing */
qemu_log_mask(LOG_GUEST_ERROR,
"gt64120: Read-only register write "
"reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
"reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break;
@ -474,7 +474,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
/* Read-only registers, do nothing */
qemu_log_mask(LOG_GUEST_ERROR,
"gt64120: Read-only register write "
"reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
"reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break;
@ -516,7 +516,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
/* Not implemented */
qemu_log_mask(LOG_UNIMP,
"gt64120: Unimplemented device register write "
"reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
"reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break;
@ -529,7 +529,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
/* Read-only registers, do nothing */
qemu_log_mask(LOG_GUEST_ERROR,
"gt64120: Read-only register write "
"reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
"reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break;
@ -566,7 +566,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
/* Not implemented */
qemu_log_mask(LOG_UNIMP,
"gt64120: Unimplemented DMA register write "
"reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
"reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break;
@ -579,7 +579,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
/* Not implemented */
qemu_log_mask(LOG_UNIMP,
"gt64120: Unimplemented timer register write "
"reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
"reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break;
@ -622,8 +622,8 @@ static void gt64120_writel(void *opaque, hwaddr addr,
case GT_PCI1_CFGDATA:
/* not implemented */
qemu_log_mask(LOG_UNIMP,
"gt64120: Unimplemented timer register write "
"reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
"gt64120: Unimplemented PCI register write "
"reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break;
case GT_PCI0_CFGADDR:
@ -643,19 +643,19 @@ static void gt64120_writel(void *opaque, hwaddr addr,
/* not really implemented */
s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
trace_gt64120_write("INTRCAUSE", size, val);
trace_gt64120_write_intreg("INTRCAUSE", size, val);
break;
case GT_INTRMASK:
s->regs[saddr] = val & 0x3c3ffffe;
trace_gt64120_write("INTRMASK", size, val);
trace_gt64120_write_intreg("INTRMASK", size, val);
break;
case GT_PCI0_ICMASK:
s->regs[saddr] = val & 0x03fffffe;
trace_gt64120_write("ICMASK", size, val);
trace_gt64120_write_intreg("ICMASK", size, val);
break;
case GT_PCI0_SERR0MASK:
s->regs[saddr] = val & 0x0000003f;
trace_gt64120_write("SERR0MASK", size, val);
trace_gt64120_write_intreg("SERR0MASK", size, val);
break;
/* Reserved when only PCI_0 is configured. */
@ -683,7 +683,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
default:
qemu_log_mask(LOG_GUEST_ERROR,
"gt64120: Illegal register write "
"reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
"reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break;
}
@ -695,9 +695,8 @@ static uint64_t gt64120_readl(void *opaque,
GT64120State *s = opaque;
PCIHostState *phb = PCI_HOST_BRIDGE(s);
uint32_t val;
uint32_t saddr;
uint32_t saddr = addr >> 2;
saddr = (addr & 0xfff) >> 2;
switch (saddr) {
/* CPU Configuration */
@ -931,19 +930,19 @@ static uint64_t gt64120_readl(void *opaque,
/* Interrupts */
case GT_INTRCAUSE:
val = s->regs[saddr];
trace_gt64120_read("INTRCAUSE", size, val);
trace_gt64120_read_intreg("INTRCAUSE", size, val);
break;
case GT_INTRMASK:
val = s->regs[saddr];
trace_gt64120_read("INTRMASK", size, val);
trace_gt64120_read_intreg("INTRMASK", size, val);
break;
case GT_PCI0_ICMASK:
val = s->regs[saddr];
trace_gt64120_read("ICMASK", size, val);
trace_gt64120_read_intreg("ICMASK", size, val);
break;
case GT_PCI0_SERR0MASK:
val = s->regs[saddr];
trace_gt64120_read("SERR0MASK", size, val);
trace_gt64120_read_intreg("SERR0MASK", size, val);
break;
/* Reserved when only PCI_0 is configured. */
@ -960,7 +959,7 @@ static uint64_t gt64120_readl(void *opaque,
val = s->regs[saddr];
qemu_log_mask(LOG_GUEST_ERROR,
"gt64120: Illegal register read "
"reg:0x03%x size:%u value:0x%0*x\n",
"reg:0x%03x size:%u value:0x%0*x\n",
saddr << 2, size, size << 1, val);
break;
}
@ -968,6 +967,7 @@ static uint64_t gt64120_readl(void *opaque,
if (!(s->regs[GT_CPU] & 0x00001000)) {
val = bswap32(val);
}
trace_gt64120_read(addr, val);
return val;
}
@ -976,6 +976,10 @@ static const MemoryRegionOps isd_mem_ops = {
.read = gt64120_readl,
.write = gt64120_writel,
.endianness = DEVICE_NATIVE_ENDIAN,
.impl = {
.min_access_size = 4,
.max_access_size = 4,
},
};
static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)
@ -1196,6 +1200,14 @@ static void gt64120_reset(DeviceState *dev)
gt64120_pci_mapping(s);
}
static void gt64120_realize(DeviceState *dev, Error **errp)
{
GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev);
memory_region_init_io(&s->ISD_mem, OBJECT(dev), &isd_mem_ops, s,
"gt64120-isd", 0x1000);
}
PCIBus *gt64120_register(qemu_irq *pic)
{
GT64120State *d;
@ -1214,8 +1226,6 @@ PCIBus *gt64120_register(qemu_irq *pic)
get_system_io(),
PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d,
"isd-mem", 0x1000);
pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");
return phb->bus;
@ -1270,6 +1280,7 @@ static void gt64120_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->realize = gt64120_realize;
dc->reset = gt64120_reset;
dc->vmsd = &vmstate_gt64120;
}

6
hw/mips/trace-events
View File

@ -1,4 +1,6 @@
# gt64xxx_pci.c
gt64120_read(const char *regname, unsigned size, uint64_t value) "gt64120 read %s size:%u value:0x%08" PRIx64
gt64120_write(const char *regname, unsigned size, uint64_t value) "gt64120 write %s size:%u value:0x%08" PRIx64
gt64120_read(uint64_t addr, uint64_t value) "gt64120 read 0x%03"PRIx64" value:0x%08" PRIx64
gt64120_write(uint64_t addr, uint64_t value) "gt64120 write 0x%03"PRIx64" value:0x%08" PRIx64
gt64120_read_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 read %s size:%u value:0x%08" PRIx64
gt64120_write_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 write %s size:%u value:0x%08" PRIx64
gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64

18
target/mips/meson.build
View File

@ -3,15 +3,17 @@ gen = [
decodetree.process('mips64r6.decode', extra_args: '--static-decode=decode_mips64r6'),
decodetree.process('msa32.decode', extra_args: '--static-decode=decode_msa32'),
decodetree.process('msa64.decode', extra_args: '--static-decode=decode_msa64'),
decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'),
]
mips_ss = ss.source_set()
mips_ss.add(gen)
mips_ss.add(files(
'cpu.c',
'gdbstub.c',
))
mips_ss.add(when: 'CONFIG_TCG', if_true: files(
mips_tcg_ss = ss.source_set()
mips_tcg_ss.add(gen)
mips_tcg_ss.add(files(
'dsp_helper.c',
'fpu_helper.c',
'lmmi_helper.c',
@ -22,7 +24,15 @@ mips_ss.add(when: 'CONFIG_TCG', if_true: files(
'tlb_helper.c',
'translate.c',
'translate_addr_const.c',
'txx9_translate.c',
))
mips_ss.add(when: ['CONFIG_TCG', 'TARGET_MIPS64'], if_true: files(
'tx79_translate.c',
))
mips_tcg_ss.add(when: 'TARGET_MIPS64', if_false: files(
'mxu_translate.c',
))
mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
mips_softmmu_ss = ss.source_set()
@ -30,11 +40,13 @@ mips_softmmu_ss.add(files(
'addr.c',
'cp0_timer.c',
'machine.c',
'mips-semi.c',
))
mips_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files(
'cp0_helper.c',
'mips-semi.c',
))
mips_ss.add_all(when: 'CONFIG_TCG', if_true: [mips_tcg_ss])
target_arch += {'mips': mips_ss}
target_softmmu_arch += {'mips': mips_softmmu_ss}

1609
target/mips/mxu_translate.c Normal file
View File

File diff suppressed because it is too large Load Diff

3665
target/mips/translate.c
View File

File diff suppressed because it is too large Load Diff

10
target/mips/translate.h
View File

@ -148,6 +148,8 @@ void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1);
bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel);
extern TCGv cpu_gpr[32], cpu_PC;
#if defined(TARGET_MIPS64)
extern TCGv_i64 cpu_gpr_hi[32];
@ -178,8 +180,16 @@ extern TCGv bcond;
/* MSA */
void msa_translate_init(void);
/* MXU */
void mxu_translate_init(void);
bool decode_ase_mxu(DisasContext *ctx, uint32_t insn);
/* decodetree generated */
bool decode_isa_rel6(DisasContext *ctx, uint32_t insn);
bool decode_ase_msa(DisasContext *ctx, uint32_t insn);
bool decode_ext_txx9(DisasContext *ctx, uint32_t insn);
#if defined(TARGET_MIPS64)
bool decode_ext_tx79(DisasContext *ctx, uint32_t insn);
#endif
#endif

39
target/mips/tx79.decode Normal file
View File

@ -0,0 +1,39 @@
# Toshiba C790's instruction set
#
# Copyright (C) 2021 Philippe Mathieu-Daudé
#
# SPDX-License-Identifier: LGPL-2.1-or-later
#
# Toshiba Appendix B C790-Specific Instruction Set Details
###########################################################################
# Named attribute sets. These are used to make nice(er) names
# when creating helpers common to those for the individual
# instruction patterns.
&rtype rs rt rd sa
###########################################################################
# Named instruction formats. These are generally used to
# reduce the amount of duplication between instruction patterns.
@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &rtype sa=0
@rt_rd ...... ..... rt:5 rd:5 ..... ...... &rtype rs=0 sa=0
@rs ...... rs:5 ..... .......... ...... &rtype rt=0 rd=0 sa=0
@rd ...... .......... rd:5 ..... ...... &rtype rs=0 rt=0 sa=0
###########################################################################
MFHI1 011100 0000000000 ..... 00000 010000 @rd
MTHI1 011100 ..... 0000000000 00000 010001 @rs
MFLO1 011100 0000000000 ..... 00000 010010 @rd
MTLO1 011100 ..... 0000000000 00000 010011 @rs
# MMI2
PCPYLD 011100 ..... ..... ..... 01110 001001 @rs_rt_rd
# MMI3
PCPYUD 011100 ..... ..... ..... 01110 101001 @rs_rt_rd
PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd

303
target/mips/tx79_translate.c Normal file
View File

@ -0,0 +1,303 @@
/*
* Toshiba TX79-specific instructions translation routines
*
* Copyright (c) 2018 Fredrik Noring
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "tcg/tcg-op.h"
#include "exec/helper-gen.h"
#include "translate.h"
/* Include the auto-generated decoder. */
#include "decode-tx79.c.inc"
/*
* Overview of the TX79-specific instruction set
* =============================================
*
* The R5900 and the C790 have 128-bit wide GPRs, where the upper 64 bits
* are only used by the specific quadword (128-bit) LQ/SQ load/store
* instructions and certain multimedia instructions (MMIs). These MMIs
* configure the 128-bit data path as two 64-bit, four 32-bit, eight 16-bit
* or sixteen 8-bit paths.
*
* Reference:
*
* The Toshiba TX System RISC TX79 Core Architecture manual,
* https://wiki.qemu.org/File:C790.pdf
*/
bool decode_ext_tx79(DisasContext *ctx, uint32_t insn)
{
if (TARGET_LONG_BITS == 64 && decode_tx79(ctx, insn)) {
return true;
}
return false;
}
/*
* Three-Operand Multiply and Multiply-Add (4 instructions)
* --------------------------------------------------------
* MADD [rd,] rs, rt Multiply/Add
* MADDU [rd,] rs, rt Multiply/Add Unsigned
* MULT [rd,] rs, rt Multiply (3-operand)
* MULTU [rd,] rs, rt Multiply Unsigned (3-operand)
*/
/*
* Multiply Instructions for Pipeline 1 (10 instructions)
* ------------------------------------------------------
* MULT1 [rd,] rs, rt Multiply Pipeline 1
* MULTU1 [rd,] rs, rt Multiply Unsigned Pipeline 1
* DIV1 rs, rt Divide Pipeline 1
* DIVU1 rs, rt Divide Unsigned Pipeline 1
* MADD1 [rd,] rs, rt Multiply-Add Pipeline 1
* MADDU1 [rd,] rs, rt Multiply-Add Unsigned Pipeline 1
* MFHI1 rd Move From HI1 Register
* MFLO1 rd Move From LO1 Register
* MTHI1 rs Move To HI1 Register
* MTLO1 rs Move To LO1 Register
*/
static bool trans_MFHI1(DisasContext *ctx, arg_rtype *a)
{
gen_store_gpr(cpu_HI[1], a->rd);
return true;
}
static bool trans_MFLO1(DisasContext *ctx, arg_rtype *a)
{
gen_store_gpr(cpu_LO[1], a->rd);
return true;
}
static bool trans_MTHI1(DisasContext *ctx, arg_rtype *a)
{
gen_load_gpr(cpu_HI[1], a->rs);
return true;
}
static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a)
{
gen_load_gpr(cpu_LO[1], a->rs);
return true;
}
/*
* Arithmetic (19 instructions)
* ----------------------------
* PADDB rd, rs, rt Parallel Add Byte
* PSUBB rd, rs, rt Parallel Subtract Byte
* PADDH rd, rs, rt Parallel Add Halfword
* PSUBH rd, rs, rt Parallel Subtract Halfword
* PADDW rd, rs, rt Parallel Add Word
* PSUBW rd, rs, rt Parallel Subtract Word
* PADSBH rd, rs, rt Parallel Add/Subtract Halfword
* PADDSB rd, rs, rt Parallel Add with Signed Saturation Byte
* PSUBSB rd, rs, rt Parallel Subtract with Signed Saturation Byte
* PADDSH rd, rs, rt Parallel Add with Signed Saturation Halfword
* PSUBSH rd, rs, rt Parallel Subtract with Signed Saturation Halfword
* PADDSW rd, rs, rt Parallel Add with Signed Saturation Word
* PSUBSW rd, rs, rt Parallel Subtract with Signed Saturation Word
* PADDUB rd, rs, rt Parallel Add with Unsigned saturation Byte
* PSUBUB rd, rs, rt Parallel Subtract with Unsigned saturation Byte
* PADDUH rd, rs, rt Parallel Add with Unsigned saturation Halfword
* PSUBUH rd, rs, rt Parallel Subtract with Unsigned saturation Halfword
* PADDUW rd, rs, rt Parallel Add with Unsigned saturation Word
* PSUBUW rd, rs, rt Parallel Subtract with Unsigned saturation Word
*/
/*
* Min/Max (4 instructions)
* ------------------------
* PMAXH rd, rs, rt Parallel Maximum Halfword
* PMINH rd, rs, rt Parallel Minimum Halfword
* PMAXW rd, rs, rt Parallel Maximum Word
* PMINW rd, rs, rt Parallel Minimum Word
*/
/*
* Absolute (2 instructions)
* -------------------------
* PABSH rd, rt Parallel Absolute Halfword
* PABSW rd, rt Parallel Absolute Word
*/
/*
* Logical (4 instructions)
* ------------------------
* PAND rd, rs, rt Parallel AND
* POR rd, rs, rt Parallel OR
* PXOR rd, rs, rt Parallel XOR
* PNOR rd, rs, rt Parallel NOR
*/
/*
* Shift (9 instructions)
* ----------------------
* PSLLH rd, rt, sa Parallel Shift Left Logical Halfword
* PSRLH rd, rt, sa Parallel Shift Right Logical Halfword
* PSRAH rd, rt, sa Parallel Shift Right Arithmetic Halfword
* PSLLW rd, rt, sa Parallel Shift Left Logical Word
* PSRLW rd, rt, sa Parallel Shift Right Logical Word
* PSRAW rd, rt, sa Parallel Shift Right Arithmetic Word
* PSLLVW rd, rt, rs Parallel Shift Left Logical Variable Word
* PSRLVW rd, rt, rs Parallel Shift Right Logical Variable Word
* PSRAVW rd, rt, rs Parallel Shift Right Arithmetic Variable Word
*/
/*
* Compare (6 instructions)
* ------------------------
* PCGTB rd, rs, rt Parallel Compare for Greater Than Byte
* PCEQB rd, rs, rt Parallel Compare for Equal Byte
* PCGTH rd, rs, rt Parallel Compare for Greater Than Halfword
* PCEQH rd, rs, rt Parallel Compare for Equal Halfword
* PCGTW rd, rs, rt Parallel Compare for Greater Than Word
* PCEQW rd, rs, rt Parallel Compare for Equal Word
*/
/*
* LZC (1 instruction)
* -------------------
* PLZCW rd, rs Parallel Leading Zero or One Count Word
*/
/*
* Quadword Load and Store (2 instructions)
* ----------------------------------------
* LQ rt, offset(base) Load Quadword
* SQ rt, offset(base) Store Quadword
*/
/*
* Multiply and Divide (19 instructions)
* -------------------------------------
* PMULTW rd, rs, rt Parallel Multiply Word
* PMULTUW rd, rs, rt Parallel Multiply Unsigned Word
* PDIVW rs, rt Parallel Divide Word
* PDIVUW rs, rt Parallel Divide Unsigned Word
* PMADDW rd, rs, rt Parallel Multiply-Add Word
* PMADDUW rd, rs, rt Parallel Multiply-Add Unsigned Word
* PMSUBW rd, rs, rt Parallel Multiply-Subtract Word
* PMULTH rd, rs, rt Parallel Multiply Halfword
* PMADDH rd, rs, rt Parallel Multiply-Add Halfword
* PMSUBH rd, rs, rt Parallel Multiply-Subtract Halfword
* PHMADH rd, rs, rt Parallel Horizontal Multiply-Add Halfword
* PHMSBH rd, rs, rt Parallel Horizontal Multiply-Subtract Halfword
* PDIVBW rs, rt Parallel Divide Broadcast Word
* PMFHI rd Parallel Move From HI Register
* PMFLO rd Parallel Move From LO Register
* PMTHI rs Parallel Move To HI Register
* PMTLO rs Parallel Move To LO Register
* PMFHL rd Parallel Move From HI/LO Register
* PMTHL rs Parallel Move To HI/LO Register
*/
/*
* Pack/Extend (11 instructions)
* -----------------------------
* PPAC5 rd, rt Parallel Pack to 5 bits
* PPACB rd, rs, rt Parallel Pack to Byte
* PPACH rd, rs, rt Parallel Pack to Halfword
* PPACW rd, rs, rt Parallel Pack to Word
* PEXT5 rd, rt Parallel Extend Upper from 5 bits
* PEXTUB rd, rs, rt Parallel Extend Upper from Byte
* PEXTLB rd, rs, rt Parallel Extend Lower from Byte
* PEXTUH rd, rs, rt Parallel Extend Upper from Halfword
* PEXTLH rd, rs, rt Parallel Extend Lower from Halfword
* PEXTUW rd, rs, rt Parallel Extend Upper from Word
* PEXTLW rd, rs, rt Parallel Extend Lower from Word
*/
/*
* Others (16 instructions)
* ------------------------
* PCPYH rd, rt Parallel Copy Halfword
* PCPYLD rd, rs, rt Parallel Copy Lower Doubleword
* PCPYUD rd, rs, rt Parallel Copy Upper Doubleword
* PREVH rd, rt Parallel Reverse Halfword
* PINTH rd, rs, rt Parallel Interleave Halfword
* PINTEH rd, rs, rt Parallel Interleave Even Halfword
* PEXEH rd, rt Parallel Exchange Even Halfword
* PEXCH rd, rt Parallel Exchange Center Halfword
* PEXEW rd, rt Parallel Exchange Even Word
* PEXCW rd, rt Parallel Exchange Center Word
* QFSRV rd, rs, rt Quadword Funnel Shift Right Variable
* MFSA rd Move from Shift Amount Register
* MTSA rs Move to Shift Amount Register
* MTSAB rs, immediate Move Byte Count to Shift Amount Register
* MTSAH rs, immediate Move Halfword Count to Shift Amount Register
* PROT3W rd, rt Parallel Rotate 3 Words
*/
/* Parallel Copy Halfword */
static bool trans_PCPYH(DisasContext *s, arg_rtype *a)
{
if (a->rd == 0) {
/* nop */
return true;
}
if (a->rt == 0) {
tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
return true;
}
tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], cpu_gpr[a->rt], 16, 16);
tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], cpu_gpr[a->rd], 32, 32);
tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rt], cpu_gpr_hi[a->rt], 16, 16);
tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], 32, 32);
return true;
}
/* Parallel Copy Lower Doubleword */
static bool trans_PCPYLD(DisasContext *s, arg_rtype *a)
{
if (a->rd == 0) {
/* nop */
return true;
}
if (a->rs == 0) {
tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
} else {
tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr[a->rs]);
}
if (a->rt == 0) {
tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
} else if (a->rd != a->rt) {
tcg_gen_mov_i64(cpu_gpr[a->rd], cpu_gpr[a->rt]);
}
return true;
}
/* Parallel Copy Upper Doubleword */
static bool trans_PCPYUD(DisasContext *s, arg_rtype *a)
{
if (a->rd == 0) {
/* nop */
return true;
}
gen_load_gpr_hi(cpu_gpr[a->rd], a->rs);
if (a->rt == 0) {
tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
} else if (a->rd != a->rt) {
tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rt]);
}
return true;
}

20
target/mips/txx9_translate.c Normal file
View File

@ -0,0 +1,20 @@
/*
* Toshiba TXx9 instructions translation routines
*
* Copyright (c) 2021 Philippe Mathieu-Daudé
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "translate.h"
bool decode_ext_txx9(DisasContext *ctx, uint32_t insn)
{
#if defined(TARGET_MIPS64)
if (decode_ext_tx79(ctx, insn)) {
return true;
}
#endif
return false;
}