From 3944d58db3fc5bf131345a21a44013bc13849a12 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Mon, 23 Mar 2020 17:22:30 +0000 Subject: [PATCH] target/arm: Assert immh != 0 in disas_simd_shift_imm MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Coverity raised a shed-load of errors cascading from inferring that clz32(immh) might yield 32, from immh might be 0. While immh cannot be 0 from encoding, it is not obvious even to a human how we've checked that: via the filtering provided by data_proc_simd[]. Reported-by: Coverity (CID 1421923, and more) Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20200320160622.8040-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 8fffb52203..032478614c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10405,6 +10405,9 @@ static void disas_simd_shift_imm(DisasContext *s, uint32_t insn) bool is_u = extract32(insn, 29, 1); bool is_q = extract32(insn, 30, 1); + /* data_proc_simd[] has sent immh == 0 to disas_simd_mod_imm. */ + assert(immh != 0); + switch (opcode) { case 0x08: /* SRI */ if (!is_u) {