mirror of https://github.com/proxmox/mirror_qemu
target-arm: Implement XScale cache lockdown operations as NOPs
XScale defines some implementation-specific coprocessor registers for doing cache lockdown operations. Since QEMU doesn't model a cache no proper implementation is possible, but NOP out the registers so that guest code like u-boot that tries to use them doesn't crash. Reported-by: <prqek@centrum.cz> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>master
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051b9980b9
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3b77157964
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@ -1578,6 +1578,21 @@ static const ARMCPRegInfo xscale_cp_reginfo[] = {
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.cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
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.cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
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.fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
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.fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
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.resetvalue = 0, },
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.resetvalue = 0, },
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/* XScale specific cache-lockdown: since we have no cache we NOP these
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* and hope the guest does not really rely on cache behaviour.
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*/
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{ .name = "XSCALE_LOCK_ICACHE_LINE",
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.cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
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.access = PL1_W, .type = ARM_CP_NOP },
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{ .name = "XSCALE_UNLOCK_ICACHE",
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.cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
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.access = PL1_W, .type = ARM_CP_NOP },
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{ .name = "XSCALE_DCACHE_LOCK",
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.cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_NOP },
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{ .name = "XSCALE_UNLOCK_DCACHE",
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.cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
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.access = PL1_W, .type = ARM_CP_NOP },
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REGINFO_SENTINEL
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REGINFO_SENTINEL
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};
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};
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