mirror of https://github.com/proxmox/mirror_qemu
target/arm: Fix Cortex-R5F MVFR values
The Cortex-R5F initfn was not correctly setting up the MVFR ID register values. Fill these in, since some subsequent patches will use ID register checks rather than CPU feature bit checks. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>master
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06db8196bb
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3de79d335c
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@ -1609,6 +1609,8 @@ static void cortex_r5f_initfn(Object *obj)
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cortex_r5_initfn(obj);
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set_feature(&cpu->env, ARM_FEATURE_VFP3);
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cpu->isar.mvfr0 = 0x10110221;
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cpu->isar.mvfr1 = 0x00000011;
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}
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static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
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