mirror of https://github.com/proxmox/mirror_qemu
target/s390x: implement mvcos instruction
This adds support for the MOVE WITH OPTIONAL SPECIFICATIONS (MVCOS) instruction. Allow to enable it for the qemu cpu model using qemu-system-s390x ... -cpu qemu,mvcos=on ... This allows to boot linux kernel that uses it for uacccess. We are missing (as for most other part) low address protection checks, PSW key / storage key checks and support for AR-mode. We fake an ADDRESSING exception when called from problem state (which seems to rely on PSW key checks to be in place) and if AR-mode is used. user mode will always see a PRIVILEDGED exception. This patch is based on an original patch by Miroslav Benes (thanks!). Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170614133819.18480-3-david@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>master
parent
c8bd95377b
commit
3e7e5e0bc1
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@ -304,6 +304,7 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);
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#undef PSW_MASK_WAIT
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#undef PSW_MASK_WAIT
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#undef PSW_MASK_PSTATE
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#undef PSW_MASK_PSTATE
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#undef PSW_MASK_ASC
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#undef PSW_MASK_ASC
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#undef PSW_SHIFT_ASC
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#undef PSW_MASK_CC
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#undef PSW_MASK_CC
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#undef PSW_MASK_PM
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#undef PSW_MASK_PM
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#undef PSW_MASK_64
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#undef PSW_MASK_64
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@ -320,6 +321,7 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);
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#define PSW_MASK_WAIT 0x0002000000000000ULL
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#define PSW_MASK_WAIT 0x0002000000000000ULL
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#define PSW_MASK_PSTATE 0x0001000000000000ULL
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#define PSW_MASK_PSTATE 0x0001000000000000ULL
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#define PSW_MASK_ASC 0x0000C00000000000ULL
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#define PSW_MASK_ASC 0x0000C00000000000ULL
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#define PSW_SHIFT_ASC 46
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#define PSW_MASK_CC 0x0000300000000000ULL
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#define PSW_MASK_CC 0x0000300000000000ULL
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#define PSW_MASK_PM 0x00000F0000000000ULL
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#define PSW_MASK_PM 0x00000F0000000000ULL
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#define PSW_MASK_64 0x0000000100000000ULL
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#define PSW_MASK_64 0x0000000100000000ULL
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@ -336,6 +338,12 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);
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#define PSW_ASC_SECONDARY 0x0000800000000000ULL
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#define PSW_ASC_SECONDARY 0x0000800000000000ULL
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#define PSW_ASC_HOME 0x0000C00000000000ULL
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#define PSW_ASC_HOME 0x0000C00000000000ULL
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/* the address space values shifted */
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#define AS_PRIMARY 0
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#define AS_ACCREG 1
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#define AS_SECONDARY 2
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#define AS_HOME 3
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/* tb flags */
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/* tb flags */
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#define FLAG_MASK_PER (PSW_MASK_PER >> 32)
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#define FLAG_MASK_PER (PSW_MASK_PER >> 32)
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@ -354,6 +362,7 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);
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/* Control register 0 bits */
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/* Control register 0 bits */
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#define CR0_LOWPROT 0x0000000010000000ULL
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#define CR0_LOWPROT 0x0000000010000000ULL
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#define CR0_SECONDARY 0x0000000004000000ULL
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#define CR0_EDAT 0x0000000000800000ULL
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#define CR0_EDAT 0x0000000000800000ULL
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/* MMU */
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/* MMU */
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@ -361,7 +370,18 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);
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#define MMU_SECONDARY_IDX 1
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#define MMU_SECONDARY_IDX 1
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#define MMU_HOME_IDX 2
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#define MMU_HOME_IDX 2
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static inline int cpu_mmu_index (CPUS390XState *env, bool ifetch)
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static inline bool psw_key_valid(CPUS390XState *env, uint8_t psw_key)
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{
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uint16_t pkm = env->cregs[3] >> 16;
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if (env->psw.mask & PSW_MASK_PSTATE) {
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/* PSW key has range 0..15, it is valid if the bit is 1 in the PKM */
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return pkm & (0x80 >> psw_key);
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}
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return true;
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}
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static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
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{
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{
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switch (env->psw.mask & PSW_MASK_ASC) {
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switch (env->psw.mask & PSW_MASK_ASC) {
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case PSW_ASC_PRIMARY:
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case PSW_ASC_PRIMARY:
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@ -682,6 +682,7 @@ static void add_qemu_cpu_model_features(S390FeatBitmap fbm)
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S390_FEAT_LONG_DISPLACEMENT_FAST,
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S390_FEAT_LONG_DISPLACEMENT_FAST,
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S390_FEAT_ETF2_ENH,
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S390_FEAT_ETF2_ENH,
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S390_FEAT_STORE_CLOCK_FAST,
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S390_FEAT_STORE_CLOCK_FAST,
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S390_FEAT_MOVE_WITH_OPTIONAL_SPEC,
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S390_FEAT_GENERAL_INSTRUCTIONS_EXT,
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S390_FEAT_GENERAL_INSTRUCTIONS_EXT,
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S390_FEAT_EXECUTE_EXT,
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S390_FEAT_EXECUTE_EXT,
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S390_FEAT_STFLE_45,
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S390_FEAT_STFLE_45,
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@ -105,6 +105,7 @@ DEF_HELPER_FLAGS_1(stfl, TCG_CALL_NO_RWG, void, env)
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DEF_HELPER_2(stfle, i32, env, i64)
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DEF_HELPER_2(stfle, i32, env, i64)
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DEF_HELPER_FLAGS_2(lpq, TCG_CALL_NO_WG, i64, env, i64)
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DEF_HELPER_FLAGS_2(lpq, TCG_CALL_NO_WG, i64, env, i64)
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DEF_HELPER_FLAGS_4(stpq, TCG_CALL_NO_WG, void, env, i64, i64, i64)
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DEF_HELPER_FLAGS_4(stpq, TCG_CALL_NO_WG, void, env, i64, i64, i64)
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DEF_HELPER_4(mvcos, i32, env, i64, i64, i64)
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#ifndef CONFIG_USER_ONLY
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#ifndef CONFIG_USER_ONLY
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DEF_HELPER_3(servc, i32, env, i64, i64)
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DEF_HELPER_3(servc, i32, env, i64, i64)
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@ -590,6 +590,8 @@
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C(0xb254, MVPG, RRE, Z, r1_o, r2_o, 0, 0, mvpg, 0)
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C(0xb254, MVPG, RRE, Z, r1_o, r2_o, 0, 0, mvpg, 0)
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/* MOVE STRING */
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/* MOVE STRING */
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C(0xb255, MVST, RRE, Z, r1_o, r2_o, 0, 0, mvst, 0)
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C(0xb255, MVST, RRE, Z, r1_o, r2_o, 0, 0, mvst, 0)
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/* MOVE WITH OPTIONAL SPECIFICATION */
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C(0xc800, MVCOS, SSF, MVCOS, la1, a2, 0, 0, mvcos, 0)
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/* MOVE WITH OFFSET */
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/* MOVE WITH OFFSET */
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/* Really format SS_b, but we pack both lengths into one argument
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/* Really format SS_b, but we pack both lengths into one argument
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for the helper call, so we might as well leave one 8-bit field. */
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for the helper call, so we might as well leave one 8-bit field. */
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@ -110,6 +110,20 @@ static inline void cpu_stsize_data_ra(CPUS390XState *env, uint64_t addr,
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}
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}
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}
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}
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static inline uint64_t wrap_address(CPUS390XState *env, uint64_t a)
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{
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if (!(env->psw.mask & PSW_MASK_64)) {
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if (!(env->psw.mask & PSW_MASK_32)) {
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/* 24-Bit mode */
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a &= 0x00ffffff;
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} else {
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/* 31-Bit mode */
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a &= 0x7fffffff;
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}
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}
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return a;
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}
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static void fast_memset(CPUS390XState *env, uint64_t dest, uint8_t byte,
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static void fast_memset(CPUS390XState *env, uint64_t dest, uint8_t byte,
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uint32_t l, uintptr_t ra)
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uint32_t l, uintptr_t ra)
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{
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{
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@ -133,6 +147,68 @@ static void fast_memset(CPUS390XState *env, uint64_t dest, uint8_t byte,
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}
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}
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}
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}
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#ifndef CONFIG_USER_ONLY
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static void fast_memmove_idx(CPUS390XState *env, uint64_t dest, uint64_t src,
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uint32_t len, int dest_idx, int src_idx,
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uintptr_t ra)
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{
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TCGMemOpIdx oi_dest = make_memop_idx(MO_UB, dest_idx);
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TCGMemOpIdx oi_src = make_memop_idx(MO_UB, src_idx);
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uint32_t len_adj;
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void *src_p;
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void *dest_p;
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uint8_t x;
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while (len > 0) {
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src = wrap_address(env, src);
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dest = wrap_address(env, dest);
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src_p = tlb_vaddr_to_host(env, src, MMU_DATA_LOAD, src_idx);
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dest_p = tlb_vaddr_to_host(env, dest, MMU_DATA_STORE, dest_idx);
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if (src_p && dest_p) {
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/* Access to both whole pages granted. */
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len_adj = adj_len_to_page(adj_len_to_page(len, src), dest);
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memmove(dest_p, src_p, len_adj);
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} else {
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/* We failed to get access to one or both whole pages. The next
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read or write access will likely fill the QEMU TLB for the
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next iteration. */
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len_adj = 1;
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x = helper_ret_ldub_mmu(env, src, oi_src, ra);
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helper_ret_stb_mmu(env, dest, x, oi_dest, ra);
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}
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src += len_adj;
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dest += len_adj;
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len -= len_adj;
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}
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}
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static int mmu_idx_from_as(uint8_t as)
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{
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switch (as) {
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case AS_PRIMARY:
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return MMU_PRIMARY_IDX;
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case AS_SECONDARY:
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return MMU_SECONDARY_IDX;
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case AS_HOME:
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return MMU_HOME_IDX;
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default:
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/* FIXME AS_ACCREG */
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g_assert_not_reached();
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}
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}
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static void fast_memmove_as(CPUS390XState *env, uint64_t dest, uint64_t src,
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uint32_t len, uint8_t dest_as, uint8_t src_as,
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uintptr_t ra)
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{
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int src_idx = mmu_idx_from_as(src_as);
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int dest_idx = mmu_idx_from_as(dest_as);
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fast_memmove_idx(env, dest, src, len, dest_idx, src_idx, ra);
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}
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#endif
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static void fast_memmove(CPUS390XState *env, uint64_t dest, uint64_t src,
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static void fast_memmove(CPUS390XState *env, uint64_t dest, uint64_t src,
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uint32_t l, uintptr_t ra)
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uint32_t l, uintptr_t ra)
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{
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{
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@ -408,20 +484,6 @@ uint32_t HELPER(clm)(CPUS390XState *env, uint32_t r1, uint32_t mask,
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return cc;
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return cc;
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}
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}
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static inline uint64_t wrap_address(CPUS390XState *env, uint64_t a)
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{
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if (!(env->psw.mask & PSW_MASK_64)) {
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if (!(env->psw.mask & PSW_MASK_32)) {
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/* 24-Bit mode */
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a &= 0x00ffffff;
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} else {
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/* 31-Bit mode */
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a &= 0x7fffffff;
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}
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}
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return a;
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}
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static inline uint64_t get_address(CPUS390XState *env, int reg)
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static inline uint64_t get_address(CPUS390XState *env, int reg)
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{
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{
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return wrap_address(env, env->regs[reg]);
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return wrap_address(env, env->regs[reg]);
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@ -1789,3 +1851,94 @@ void HELPER(ex)(CPUS390XState *env, uint32_t ilen, uint64_t r1, uint64_t addr)
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that requires such execution. */
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that requires such execution. */
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env->ex_value = insn | ilen;
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env->ex_value = insn | ilen;
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}
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}
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uint32_t HELPER(mvcos)(CPUS390XState *env, uint64_t dest, uint64_t src,
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uint64_t len)
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{
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const uint8_t psw_key = (env->psw.mask & PSW_MASK_KEY) >> PSW_SHIFT_KEY;
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const uint8_t psw_as = (env->psw.mask & PSW_MASK_ASC) >> PSW_SHIFT_ASC;
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const uint64_t r0 = env->regs[0];
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const uintptr_t ra = GETPC();
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CPUState *cs = CPU(s390_env_get_cpu(env));
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uint8_t dest_key, dest_as, dest_k, dest_a;
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uint8_t src_key, src_as, src_k, src_a;
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uint64_t val;
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int cc = 0;
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HELPER_LOG("%s dest %" PRIx64 ", src %" PRIx64 ", len %" PRIx64 "\n",
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__func__, dest, src, len);
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if (!(env->psw.mask & PSW_MASK_DAT)) {
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cpu_restore_state(cs, ra);
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program_interrupt(env, PGM_SPECIAL_OP, 6);
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}
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/* OAC (operand access control) for the first operand -> dest */
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val = (r0 & 0xffff0000ULL) >> 16;
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dest_key = (val >> 12) & 0xf;
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dest_as = (val >> 6) & 0x3;
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dest_k = (val >> 1) & 0x1;
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dest_a = val & 0x1;
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/* OAC (operand access control) for the second operand -> src */
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val = (r0 & 0x0000ffffULL);
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src_key = (val >> 12) & 0xf;
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src_as = (val >> 6) & 0x3;
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src_k = (val >> 1) & 0x1;
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src_a = val & 0x1;
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if (!dest_k) {
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dest_key = psw_key;
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}
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if (!src_k) {
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src_key = psw_key;
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}
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if (!dest_a) {
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dest_as = psw_as;
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}
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if (!src_a) {
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src_as = psw_as;
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}
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if (dest_a && dest_as == AS_HOME && (env->psw.mask & PSW_MASK_PSTATE)) {
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cpu_restore_state(cs, ra);
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program_interrupt(env, PGM_SPECIAL_OP, 6);
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}
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if (!(env->cregs[0] & CR0_SECONDARY) &&
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(dest_as == AS_SECONDARY || src_as == AS_SECONDARY)) {
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cpu_restore_state(cs, ra);
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program_interrupt(env, PGM_SPECIAL_OP, 6);
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}
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if (!psw_key_valid(env, dest_key) || !psw_key_valid(env, src_key)) {
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cpu_restore_state(cs, ra);
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program_interrupt(env, PGM_PRIVILEGED, 6);
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}
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len = wrap_length(env, len);
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if (len > 4096) {
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cc = 3;
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len = 4096;
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}
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/* FIXME: AR-mode and proper problem state mode (using PSW keys) missing */
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if (src_as == AS_ACCREG || dest_as == AS_ACCREG ||
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(env->psw.mask & PSW_MASK_PSTATE)) {
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qemu_log_mask(LOG_UNIMP, "%s: AR-mode and PSTATE support missing\n",
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__func__);
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cpu_restore_state(cs, ra);
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program_interrupt(env, PGM_ADDRESSING, 6);
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}
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/* FIXME: a) LAP
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* b) Access using correct keys
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* c) AR-mode
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*/
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#ifdef CONFIG_USER_ONLY
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/* psw keys are never valid in user mode, we will never reach this */
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g_assert_not_reached();
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#else
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fast_memmove_as(env, dest, src, len, dest_as, src_as, ra);
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#endif
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return cc;
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}
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@ -3041,6 +3041,14 @@ static ExitStatus op_mvclu(DisasContext *s, DisasOps *o)
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return NO_EXIT;
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return NO_EXIT;
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}
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}
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static ExitStatus op_mvcos(DisasContext *s, DisasOps *o)
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{
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int r3 = get_field(s->fields, r3);
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gen_helper_mvcos(cc_op, cpu_env, o->addr1, o->in2, regs[r3]);
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||||||
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set_cc_static(s);
|
||||||
|
return NO_EXIT;
|
||||||
|
}
|
||||||
|
|
||||||
#ifndef CONFIG_USER_ONLY
|
#ifndef CONFIG_USER_ONLY
|
||||||
static ExitStatus op_mvcp(DisasContext *s, DisasOps *o)
|
static ExitStatus op_mvcp(DisasContext *s, DisasOps *o)
|
||||||
{
|
{
|
||||||
|
@ -5413,6 +5421,7 @@ enum DisasInsnEnum {
|
||||||
#define FAC_SCF S390_FEAT_STORE_CLOCK_FAST
|
#define FAC_SCF S390_FEAT_STORE_CLOCK_FAST
|
||||||
#define FAC_SFLE S390_FEAT_STFLE
|
#define FAC_SFLE S390_FEAT_STFLE
|
||||||
#define FAC_ILA S390_FEAT_STFLE_45 /* interlocked-access-facility 1 */
|
#define FAC_ILA S390_FEAT_STFLE_45 /* interlocked-access-facility 1 */
|
||||||
|
#define FAC_MVCOS S390_FEAT_MOVE_WITH_OPTIONAL_SPEC
|
||||||
#define FAC_LPP S390_FEAT_SET_PROGRAM_PARAMETERS /* load-program-parameter */
|
#define FAC_LPP S390_FEAT_SET_PROGRAM_PARAMETERS /* load-program-parameter */
|
||||||
#define FAC_DAT_ENH S390_FEAT_DAT_ENH
|
#define FAC_DAT_ENH S390_FEAT_DAT_ENH
|
||||||
#define FAC_E2 S390_FEAT_EXTENDED_TRANSLATION_2
|
#define FAC_E2 S390_FEAT_EXTENDED_TRANSLATION_2
|
||||||
|
|
Loading…
Reference in New Issue