mirror of https://github.com/proxmox/mirror_qemu
target/m68k: add DisasContext parameter to gen_extend()
This parameter will be needed to manage automatic release of temporary allocated TCG variables. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180319113544.704-2-laurent@vivier.eu>master
parent
55901900ec
commit
3f215a147b
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@ -617,7 +617,7 @@ static void gen_flush_flags(DisasContext *s)
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s->cc_op = CC_OP_FLAGS;
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s->cc_op = CC_OP_FLAGS;
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}
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}
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static inline TCGv gen_extend(TCGv val, int opsize, int sign)
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static inline TCGv gen_extend(DisasContext *s, TCGv val, int opsize, int sign)
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{
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{
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TCGv tmp;
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TCGv tmp;
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@ -811,7 +811,7 @@ static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0,
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gen_partset_reg(opsize, reg, val);
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gen_partset_reg(opsize, reg, val);
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return store_dummy;
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return store_dummy;
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} else {
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} else {
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return gen_extend(reg, opsize, what == EA_LOADS);
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return gen_extend(s, reg, opsize, what == EA_LOADS);
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}
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}
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case 1: /* Address register direct. */
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case 1: /* Address register direct. */
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reg = get_areg(s, reg0);
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reg = get_areg(s, reg0);
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@ -819,7 +819,7 @@ static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0,
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tcg_gen_mov_i32(reg, val);
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tcg_gen_mov_i32(reg, val);
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return store_dummy;
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return store_dummy;
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} else {
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} else {
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return gen_extend(reg, opsize, what == EA_LOADS);
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return gen_extend(s, reg, opsize, what == EA_LOADS);
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}
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}
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case 2: /* Indirect register */
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case 2: /* Indirect register */
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reg = get_areg(s, reg0);
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reg = get_areg(s, reg0);
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@ -1759,8 +1759,8 @@ DISAS_INSN(abcd_reg)
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gen_flush_flags(s); /* !Z is sticky */
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gen_flush_flags(s); /* !Z is sticky */
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src = gen_extend(DREG(insn, 0), OS_BYTE, 0);
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src = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
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dest = gen_extend(DREG(insn, 9), OS_BYTE, 0);
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dest = gen_extend(s, DREG(insn, 9), OS_BYTE, 0);
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bcd_add(dest, src);
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bcd_add(dest, src);
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gen_partset_reg(OS_BYTE, DREG(insn, 9), dest);
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gen_partset_reg(OS_BYTE, DREG(insn, 9), dest);
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@ -1794,8 +1794,8 @@ DISAS_INSN(sbcd_reg)
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gen_flush_flags(s); /* !Z is sticky */
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gen_flush_flags(s); /* !Z is sticky */
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src = gen_extend(DREG(insn, 0), OS_BYTE, 0);
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src = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
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dest = gen_extend(DREG(insn, 9), OS_BYTE, 0);
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dest = gen_extend(s, DREG(insn, 9), OS_BYTE, 0);
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bcd_sub(dest, src);
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bcd_sub(dest, src);
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@ -1856,7 +1856,7 @@ DISAS_INSN(addsub)
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add = (insn & 0x4000) != 0;
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add = (insn & 0x4000) != 0;
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opsize = insn_opsize(insn);
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opsize = insn_opsize(insn);
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reg = gen_extend(DREG(insn, 9), opsize, 1);
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reg = gen_extend(s, DREG(insn, 9), opsize, 1);
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dest = tcg_temp_new();
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dest = tcg_temp_new();
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if (insn & 0x100) {
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if (insn & 0x100) {
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SRC_EA(env, tmp, opsize, 1, &addr);
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SRC_EA(env, tmp, opsize, 1, &addr);
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@ -2386,7 +2386,7 @@ DISAS_INSN(cas)
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return;
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return;
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}
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}
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cmp = gen_extend(DREG(ext, 0), opsize, 1);
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cmp = gen_extend(s, DREG(ext, 0), opsize, 1);
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/* if <EA> == Dc then
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/* if <EA> == Dc then
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* <EA> = Du
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* <EA> = Du
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@ -3055,7 +3055,7 @@ DISAS_INSN(or)
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int opsize;
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int opsize;
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opsize = insn_opsize(insn);
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opsize = insn_opsize(insn);
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reg = gen_extend(DREG(insn, 9), opsize, 0);
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reg = gen_extend(s, DREG(insn, 9), opsize, 0);
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dest = tcg_temp_new();
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dest = tcg_temp_new();
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if (insn & 0x100) {
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if (insn & 0x100) {
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SRC_EA(env, src, opsize, 0, &addr);
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SRC_EA(env, src, opsize, 0, &addr);
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@ -3120,8 +3120,8 @@ DISAS_INSN(subx_reg)
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opsize = insn_opsize(insn);
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opsize = insn_opsize(insn);
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src = gen_extend(DREG(insn, 0), opsize, 1);
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src = gen_extend(s, DREG(insn, 0), opsize, 1);
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dest = gen_extend(DREG(insn, 9), opsize, 1);
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dest = gen_extend(s, DREG(insn, 9), opsize, 1);
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gen_subx(s, src, dest, opsize);
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gen_subx(s, src, dest, opsize);
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@ -3176,7 +3176,7 @@ DISAS_INSN(cmp)
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opsize = insn_opsize(insn);
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opsize = insn_opsize(insn);
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SRC_EA(env, src, opsize, 1, NULL);
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SRC_EA(env, src, opsize, 1, NULL);
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reg = gen_extend(DREG(insn, 9), opsize, 1);
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reg = gen_extend(s, DREG(insn, 9), opsize, 1);
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gen_update_cc_cmp(s, reg, src, opsize);
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gen_update_cc_cmp(s, reg, src, opsize);
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}
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}
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@ -3329,8 +3329,8 @@ DISAS_INSN(addx_reg)
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opsize = insn_opsize(insn);
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opsize = insn_opsize(insn);
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dest = gen_extend(DREG(insn, 9), opsize, 1);
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dest = gen_extend(s, DREG(insn, 9), opsize, 1);
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src = gen_extend(DREG(insn, 0), opsize, 1);
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src = gen_extend(s, DREG(insn, 0), opsize, 1);
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gen_addx(s, src, dest, opsize);
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gen_addx(s, src, dest, opsize);
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@ -3369,7 +3369,7 @@ static inline void shift_im(DisasContext *s, uint16_t insn, int opsize)
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int logical = insn & 8;
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int logical = insn & 8;
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int left = insn & 0x100;
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int left = insn & 0x100;
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int bits = opsize_bytes(opsize) * 8;
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int bits = opsize_bytes(opsize) * 8;
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TCGv reg = gen_extend(DREG(insn, 0), opsize, !logical);
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TCGv reg = gen_extend(s, DREG(insn, 0), opsize, !logical);
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if (count == 0) {
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if (count == 0) {
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count = 8;
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count = 8;
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@ -3419,7 +3419,7 @@ static inline void shift_reg(DisasContext *s, uint16_t insn, int opsize)
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int logical = insn & 8;
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int logical = insn & 8;
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int left = insn & 0x100;
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int left = insn & 0x100;
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int bits = opsize_bytes(opsize) * 8;
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int bits = opsize_bytes(opsize) * 8;
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TCGv reg = gen_extend(DREG(insn, 0), opsize, !logical);
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TCGv reg = gen_extend(s, DREG(insn, 0), opsize, !logical);
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TCGv s32;
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TCGv s32;
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TCGv_i64 t64, s64;
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TCGv_i64 t64, s64;
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@ -3556,7 +3556,7 @@ DISAS_INSN(shift_mem)
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while M68000 sets if the most significant bit is changed at
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while M68000 sets if the most significant bit is changed at
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any time during the shift operation */
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any time during the shift operation */
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if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
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if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
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src = gen_extend(src, OS_WORD, 1);
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src = gen_extend(s, src, OS_WORD, 1);
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tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src);
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tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src);
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}
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}
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} else {
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} else {
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@ -3789,7 +3789,7 @@ DISAS_INSN(rotate8_im)
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TCGv shift;
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TCGv shift;
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int tmp;
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int tmp;
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reg = gen_extend(DREG(insn, 0), OS_BYTE, 0);
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reg = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
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tmp = (insn >> 9) & 7;
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tmp = (insn >> 9) & 7;
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if (tmp == 0) {
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if (tmp == 0) {
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@ -3816,7 +3816,7 @@ DISAS_INSN(rotate16_im)
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TCGv shift;
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TCGv shift;
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int tmp;
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int tmp;
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reg = gen_extend(DREG(insn, 0), OS_WORD, 0);
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reg = gen_extend(s, DREG(insn, 0), OS_WORD, 0);
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tmp = (insn >> 9) & 7;
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tmp = (insn >> 9) & 7;
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if (tmp == 0) {
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if (tmp == 0) {
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tmp = 8;
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tmp = 8;
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@ -3876,7 +3876,7 @@ DISAS_INSN(rotate8_reg)
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TCGv t0, t1;
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TCGv t0, t1;
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int left = (insn & 0x100);
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int left = (insn & 0x100);
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reg = gen_extend(DREG(insn, 0), OS_BYTE, 0);
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reg = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
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src = DREG(insn, 9);
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src = DREG(insn, 9);
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/* shift in [0..63] */
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/* shift in [0..63] */
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t0 = tcg_temp_new_i32();
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t0 = tcg_temp_new_i32();
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@ -3911,7 +3911,7 @@ DISAS_INSN(rotate16_reg)
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TCGv t0, t1;
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TCGv t0, t1;
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int left = (insn & 0x100);
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int left = (insn & 0x100);
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reg = gen_extend(DREG(insn, 0), OS_WORD, 0);
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reg = gen_extend(s, DREG(insn, 0), OS_WORD, 0);
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src = DREG(insn, 9);
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src = DREG(insn, 9);
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/* shift in [0..63] */
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/* shift in [0..63] */
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t0 = tcg_temp_new_i32();
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t0 = tcg_temp_new_i32();
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@ -4353,7 +4353,7 @@ DISAS_INSN(chk)
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return;
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return;
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}
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}
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SRC_EA(env, src, opsize, 1, NULL);
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SRC_EA(env, src, opsize, 1, NULL);
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reg = gen_extend(DREG(insn, 9), opsize, 1);
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reg = gen_extend(s, DREG(insn, 9), opsize, 1);
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gen_flush_flags(s);
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gen_flush_flags(s);
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gen_helper_chk(cpu_env, reg, src);
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gen_helper_chk(cpu_env, reg, src);
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