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hw/cxl: Update link register definitions. 

Not actually implemented, but we need to reserve more space for
the larger version of the structure in CXL r3.1.

Reviewed-by: Fan Ni <fan.ni@samsung.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240126121636.24611-3-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
master
Jonathan Cameron 2024-01-26 12:16:33 +00:00 committed by Michael S. Tsirkin
parent ae243dbfc4
commit 40ecac10c0
1 changed files with 2 additions and 2 deletions
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4
include/hw/cxl/cxl_component.h
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@ -104,10 +104,10 @@ REG32(CXL_RAS_ERR_HEADER0, CXL_RAS_REGISTERS_OFFSET + 0x18)
(CXL_RAS_REGISTERS_OFFSET + CXL_RAS_REGISTERS_SIZE)
#define CXL_SEC_REGISTERS_SIZE 0 /* We don't implement 1.1 downstream ports */
/* 8.2.5.11 - CXL Link Capability Structure */
/* CXL r3.1 Section 8.2.4.19: CXL Link Capability Structure */
#define CXL_LINK_REGISTERS_OFFSET \
(CXL_SEC_REGISTERS_OFFSET + CXL_SEC_REGISTERS_SIZE)
#define CXL_LINK_REGISTERS_SIZE 0x38
#define CXL_LINK_REGISTERS_SIZE 0x50
/* CXL r3.1 Section 8.2.4.20: CXL HDM Decoder Capability Structure */
#define HDM_DECODE_MAX 10 /* Maximum decoders for Devices */