mirror of https://github.com/proxmox/mirror_qemu
Add periodic timer implementation.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2846 c046a42c-6fe2-441c-8c8c-71466251a162master
parent
0ff596d02f
commit
423f0742a8
157
hw/arm_timer.c
157
hw/arm_timer.c
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@ -22,114 +22,24 @@
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#define TIMER_CTRL_ENABLE (1 << 7)
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#define TIMER_CTRL_ENABLE (1 << 7)
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typedef struct {
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typedef struct {
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int64_t next_time;
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ptimer_state *timer;
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int64_t expires;
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int64_t loaded;
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QEMUTimer *timer;
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uint32_t control;
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uint32_t control;
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uint32_t count;
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uint32_t limit;
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uint32_t limit;
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int raw_freq;
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int freq;
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int freq;
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int int_level;
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int int_level;
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qemu_irq irq;
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qemu_irq irq;
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} arm_timer_state;
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} arm_timer_state;
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/* Calculate the new expiry time of the given timer. */
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static void arm_timer_reload(arm_timer_state *s)
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{
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int64_t delay;
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s->loaded = s->expires;
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delay = muldiv64(s->count, ticks_per_sec, s->freq);
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if (delay == 0)
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delay = 1;
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s->expires += delay;
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}
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/* Check all active timers, and schedule the next timer interrupt. */
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/* Check all active timers, and schedule the next timer interrupt. */
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static void arm_timer_update(arm_timer_state *s, int64_t now)
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static void arm_timer_update(arm_timer_state *s)
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{
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{
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int64_t next;
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/* Ignore disabled timers. */
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if ((s->control & TIMER_CTRL_ENABLE) == 0)
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return;
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/* Ignore expired one-shot timers. */
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if (s->count == 0 && (s->control & TIMER_CTRL_ONESHOT))
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return;
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if (s->expires - now <= 0) {
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/* Timer has expired. */
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s->int_level = 1;
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if (s->control & TIMER_CTRL_ONESHOT) {
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/* One-shot. */
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s->count = 0;
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} else {
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if ((s->control & TIMER_CTRL_PERIODIC) == 0) {
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/* Free running. */
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if (s->control & TIMER_CTRL_32BIT)
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s->count = 0xffffffff;
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else
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s->count = 0xffff;
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} else {
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/* Periodic. */
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s->count = s->limit;
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}
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}
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}
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while (s->expires - now <= 0) {
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arm_timer_reload(s);
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}
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/* Update interrupts. */
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/* Update interrupts. */
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if (s->int_level && (s->control & TIMER_CTRL_IE)) {
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if (s->int_level && (s->control & TIMER_CTRL_IE)) {
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qemu_irq_raise(s->irq);
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qemu_irq_raise(s->irq);
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} else {
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} else {
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qemu_irq_lower(s->irq);
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qemu_irq_lower(s->irq);
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}
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}
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next = now;
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if (next - s->expires < 0)
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next = s->expires;
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/* Schedule the next timer interrupt. */
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if (next == now) {
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qemu_del_timer(s->timer);
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s->next_time = 0;
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} else if (next != s->next_time) {
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qemu_mod_timer(s->timer, next);
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s->next_time = next;
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}
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}
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/* Return the current value of the timer. */
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static uint32_t arm_timer_getcount(arm_timer_state *s, int64_t now)
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{
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int64_t left;
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int64_t period;
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if (s->count == 0)
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return 0;
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if ((s->control & TIMER_CTRL_ENABLE) == 0)
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return s->count;
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left = s->expires - now;
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period = s->expires - s->loaded;
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/* If the timer should have expired then return 0. This can happen
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when the host timer signal doesnt occur immediately. It's better to
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have a timer appear to sit at zero for a while than have it wrap
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around before the guest interrupt is raised. */
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/* ??? Could we trigger the interrupt here? */
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if (left < 0)
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return 0;
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/* We need to calculate count * elapsed / period without overfowing.
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Scale both elapsed and period so they fit in a 32-bit int. */
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while (period != (int32_t)period) {
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period >>= 1;
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left >>= 1;
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}
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return ((uint64_t)s->count * (uint64_t)(int32_t)left)
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/ (int32_t)period;
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}
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}
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uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
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uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
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@ -141,7 +51,7 @@ uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
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case 6: /* TimerBGLoad */
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case 6: /* TimerBGLoad */
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return s->limit;
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return s->limit;
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case 1: /* TimerValue */
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case 1: /* TimerValue */
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return arm_timer_getcount(s, qemu_get_clock(vm_clock));
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return ptimer_get_count(s->timer);
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case 2: /* TimerControl */
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case 2: /* TimerControl */
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return s->control;
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return s->control;
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case 4: /* TimerRIS */
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case 4: /* TimerRIS */
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@ -151,24 +61,40 @@ uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
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return 0;
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return 0;
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return s->int_level;
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return s->int_level;
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default:
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default:
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cpu_abort (cpu_single_env, "arm_timer_read: Bad offset %x\n", offset);
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cpu_abort (cpu_single_env, "arm_timer_read: Bad offset %x\n",
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(int)offset);
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return 0;
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return 0;
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}
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}
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}
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}
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/* Reset the timer limit after settings have changed. */
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static void arm_timer_recalibrate(arm_timer_state *s, int reload)
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{
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uint32_t limit;
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if ((s->control & TIMER_CTRL_PERIODIC) == 0) {
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/* Free running. */
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if (s->control & TIMER_CTRL_32BIT)
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limit = 0xffffffff;
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else
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limit = 0xffff;
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} else {
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/* Periodic. */
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limit = s->limit;
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}
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ptimer_set_limit(s->timer, limit, reload);
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}
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static void arm_timer_write(void *opaque, target_phys_addr_t offset,
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static void arm_timer_write(void *opaque, target_phys_addr_t offset,
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uint32_t value)
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uint32_t value)
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{
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{
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arm_timer_state *s = (arm_timer_state *)opaque;
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arm_timer_state *s = (arm_timer_state *)opaque;
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int64_t now;
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int freq;
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now = qemu_get_clock(vm_clock);
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switch (offset >> 2) {
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switch (offset >> 2) {
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case 0: /* TimerLoad */
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case 0: /* TimerLoad */
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s->limit = value;
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s->limit = value;
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s->count = value;
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arm_timer_recalibrate(s, 1);
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s->expires = now;
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arm_timer_reload(s);
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break;
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break;
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case 1: /* TimerValue */
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case 1: /* TimerValue */
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/* ??? Linux seems to want to write to this readonly register.
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/* ??? Linux seems to want to write to this readonly register.
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@ -179,19 +105,20 @@ static void arm_timer_write(void *opaque, target_phys_addr_t offset,
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/* Pause the timer if it is running. This may cause some
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/* Pause the timer if it is running. This may cause some
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inaccuracy dure to rounding, but avoids a whole lot of other
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inaccuracy dure to rounding, but avoids a whole lot of other
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messyness. */
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messyness. */
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s->count = arm_timer_getcount(s, now);
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ptimer_stop(s->timer);
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}
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}
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s->control = value;
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s->control = value;
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s->freq = s->raw_freq;
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freq = s->freq;
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/* ??? Need to recalculate expiry time after changing divisor. */
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/* ??? Need to recalculate expiry time after changing divisor. */
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switch ((value >> 2) & 3) {
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switch ((value >> 2) & 3) {
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case 1: s->freq >>= 4; break;
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case 1: freq >>= 4; break;
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case 2: s->freq >>= 8; break;
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case 2: freq >>= 8; break;
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}
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}
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arm_timer_recalibrate(s, 0);
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ptimer_set_freq(s->timer, freq);
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if (s->control & TIMER_CTRL_ENABLE) {
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if (s->control & TIMER_CTRL_ENABLE) {
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/* Restart the timer if still enabled. */
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/* Restart the timer if still enabled. */
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s->expires = now;
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ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0);
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arm_timer_reload(s);
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}
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}
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break;
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break;
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case 3: /* TimerIntClr */
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case 3: /* TimerIntClr */
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break;
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break;
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case 6: /* TimerBGLoad */
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case 6: /* TimerBGLoad */
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s->limit = value;
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s->limit = value;
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arm_timer_recalibrate(s, 0);
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break;
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break;
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default:
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default:
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cpu_abort (cpu_single_env, "arm_timer_write: Bad offset %x\n", offset);
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cpu_abort (cpu_single_env, "arm_timer_write: Bad offset %x\n",
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(int)offset);
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}
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}
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arm_timer_update(s, now);
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arm_timer_update(s);
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}
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}
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static void arm_timer_tick(void *opaque)
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static void arm_timer_tick(void *opaque)
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{
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{
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int64_t now;
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arm_timer_state *s = (arm_timer_state *)opaque;
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s->int_level = 1;
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now = qemu_get_clock(vm_clock);
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arm_timer_update(s);
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arm_timer_update((arm_timer_state *)opaque, now);
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}
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}
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static void *arm_timer_init(uint32_t freq, qemu_irq irq)
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static void *arm_timer_init(uint32_t freq, qemu_irq irq)
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{
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{
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arm_timer_state *s;
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arm_timer_state *s;
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QEMUBH *bh;
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s = (arm_timer_state *)qemu_mallocz(sizeof(arm_timer_state));
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s = (arm_timer_state *)qemu_mallocz(sizeof(arm_timer_state));
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s->irq = irq;
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s->irq = irq;
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s->raw_freq = s->freq = 1000000;
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s->freq = freq;
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s->control = TIMER_CTRL_IE;
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s->control = TIMER_CTRL_IE;
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s->count = 0xffffffff;
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s->timer = qemu_new_timer(vm_clock, arm_timer_tick, s);
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bh = qemu_bh_new(arm_timer_tick, s);
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s->timer = ptimer_init(bh);
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/* ??? Save/restore. */
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/* ??? Save/restore. */
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return s;
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return s;
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}
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}
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@ -0,0 +1,164 @@
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/*
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* General purpose implementation of a simple periodic countdown timer.
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*
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* Copyright (c) 2007 CodeSourcery.
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*
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* This code is licenced under the GNU LGPL.
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*/
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#include "vl.h"
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struct ptimer_state
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{
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int enabled; /* 0 = disabled, 1 = periodic, 2 = oneshot. */
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uint32_t limit;
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uint32_t delta;
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uint32_t period_frac;
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int64_t period;
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int64_t last_event;
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int64_t next_event;
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QEMUBH *bh;
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QEMUTimer *timer;
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};
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/* Use a bottom-half routine to avoid reentrancy issues. */
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static void ptimer_trigger(ptimer_state *s)
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{
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if (s->bh) {
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qemu_bh_schedule(s->bh);
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}
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}
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static void ptimer_reload(ptimer_state *s)
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{
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if (s->delta == 0) {
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ptimer_trigger(s);
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s->delta = s->limit;
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}
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if (s->delta == 0 || s->period == 0) {
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fprintf(stderr, "Timer with period zero, disabling\n");
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s->enabled = 0;
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return;
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}
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s->last_event = s->next_event;
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s->next_event = s->last_event + s->delta * s->period;
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if (s->period_frac) {
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s->next_event += ((int64_t)s->period_frac * s->delta) >> 32;
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}
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qemu_mod_timer(s->timer, s->next_event);
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}
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static void ptimer_tick(void *opaque)
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{
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ptimer_state *s = (ptimer_state *)opaque;
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ptimer_trigger(s);
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s->delta = 0;
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if (s->enabled == 2) {
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s->enabled = 0;
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} else {
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ptimer_reload(s);
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}
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}
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uint32_t ptimer_get_count(ptimer_state *s)
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{
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int64_t now;
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uint32_t counter;
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if (s->enabled) {
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now = qemu_get_clock(vm_clock);
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/* Figure out the current counter value. */
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if (now - s->next_event > 0
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|| s->period == 0) {
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/* Prevent timer underflowing if it should already have
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triggered. */
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counter = 0;
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} else {
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int64_t rem;
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int64_t div;
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rem = s->next_event - now;
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div = s->period;
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counter = rem / div;
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}
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} else {
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counter = s->delta;
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}
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return counter;
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}
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void ptimer_set_count(ptimer_state *s, uint32_t count)
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{
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s->delta = count;
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if (s->enabled) {
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s->next_event = qemu_get_clock(vm_clock);
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ptimer_reload(s);
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}
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}
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void ptimer_run(ptimer_state *s, int oneshot)
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{
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if (s->period == 0) {
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fprintf(stderr, "Timer with period zero, disabling\n");
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return;
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}
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s->enabled = oneshot ? 2 : 1;
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s->next_event = qemu_get_clock(vm_clock);
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ptimer_reload(s);
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}
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/* Pause a timer. Note that this may cause it to "loose" time, even if it
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is immediately restarted. */
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void ptimer_stop(ptimer_state *s)
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{
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if (!s->enabled)
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return;
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s->delta = ptimer_get_count(s);
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qemu_del_timer(s->timer);
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s->enabled = 0;
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}
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/* Set counter increment interval in nanoseconds. */
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void ptimer_set_period(ptimer_state *s, int64_t period)
|
||||||
|
{
|
||||||
|
if (s->enabled) {
|
||||||
|
fprintf(stderr, "FIXME: ptimer_set_period with running timer");
|
||||||
|
}
|
||||||
|
s->period = period;
|
||||||
|
s->period_frac = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Set counter frequency in Hz. */
|
||||||
|
void ptimer_set_freq(ptimer_state *s, uint32_t freq)
|
||||||
|
{
|
||||||
|
if (s->enabled) {
|
||||||
|
fprintf(stderr, "FIXME: ptimer_set_freq with running timer");
|
||||||
|
}
|
||||||
|
s->period = 1000000000ll / freq;
|
||||||
|
s->period_frac = (1000000000ll << 32) / freq;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Set the initial countdown value. If reload is nonzero then also set
|
||||||
|
count = limit. */
|
||||||
|
void ptimer_set_limit(ptimer_state *s, uint32_t limit, int reload)
|
||||||
|
{
|
||||||
|
if (s->enabled) {
|
||||||
|
fprintf(stderr, "FIXME: ptimer_set_limit with running timer");
|
||||||
|
}
|
||||||
|
s->limit = limit;
|
||||||
|
if (reload)
|
||||||
|
s->delta = limit;
|
||||||
|
}
|
||||||
|
|
||||||
|
ptimer_state *ptimer_init(QEMUBH *bh)
|
||||||
|
{
|
||||||
|
ptimer_state *s;
|
||||||
|
|
||||||
|
s = (ptimer_state *)qemu_mallocz(sizeof(ptimer_state));
|
||||||
|
s->bh = bh;
|
||||||
|
s->timer = qemu_new_timer(vm_clock, ptimer_tick, s);
|
||||||
|
return s;
|
||||||
|
}
|
||||||
|
|
6
vl.c
6
vl.c
|
@ -6322,7 +6322,6 @@ void main_loop_wait(int timeout)
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
qemu_aio_poll();
|
qemu_aio_poll();
|
||||||
qemu_bh_poll();
|
|
||||||
|
|
||||||
if (vm_running) {
|
if (vm_running) {
|
||||||
qemu_run_timers(&active_timers[QEMU_TIMER_VIRTUAL],
|
qemu_run_timers(&active_timers[QEMU_TIMER_VIRTUAL],
|
||||||
|
@ -6334,6 +6333,11 @@ void main_loop_wait(int timeout)
|
||||||
/* real time timers */
|
/* real time timers */
|
||||||
qemu_run_timers(&active_timers[QEMU_TIMER_REALTIME],
|
qemu_run_timers(&active_timers[QEMU_TIMER_REALTIME],
|
||||||
qemu_get_clock(rt_clock));
|
qemu_get_clock(rt_clock));
|
||||||
|
|
||||||
|
/* Check bottom-halves last in case any of the earlier events triggered
|
||||||
|
them. */
|
||||||
|
qemu_bh_poll();
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static CPUState *cur_cpu;
|
static CPUState *cur_cpu;
|
||||||
|
|
Loading…
Reference in New Issue