mirror of https://github.com/proxmox/mirror_qemu
target-arm: A64: add support for 1-src REV insns
This adds support for C5.6.149 REV, C5.6.151 REV32, C5.6.150 REV16. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>master
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82e14b02a2
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453232096c
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@ -1080,6 +1080,73 @@ static void handle_rbit(DisasContext *s, unsigned int sf,
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}
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}
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}
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}
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/* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
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static void handle_rev64(DisasContext *s, unsigned int sf,
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unsigned int rn, unsigned int rd)
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{
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if (!sf) {
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unallocated_encoding(s);
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return;
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}
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tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn));
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}
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/* C5.6.149 REV with sf==0, opcode==2
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* C5.6.151 REV32 (sf==1, opcode==2)
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*/
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static void handle_rev32(DisasContext *s, unsigned int sf,
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unsigned int rn, unsigned int rd)
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{
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TCGv_i64 tcg_rd = cpu_reg(s, rd);
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if (sf) {
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TCGv_i64 tcg_tmp = tcg_temp_new_i64();
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TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
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/* bswap32_i64 requires zero high word */
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tcg_gen_ext32u_i64(tcg_tmp, tcg_rn);
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tcg_gen_bswap32_i64(tcg_rd, tcg_tmp);
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tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32);
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tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp);
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tcg_gen_concat32_i64(tcg_rd, tcg_rd, tcg_tmp);
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tcg_temp_free_i64(tcg_tmp);
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} else {
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tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rn));
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tcg_gen_bswap32_i64(tcg_rd, tcg_rd);
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}
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}
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/* C5.6.150 REV16 (opcode==1) */
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static void handle_rev16(DisasContext *s, unsigned int sf,
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unsigned int rn, unsigned int rd)
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{
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TCGv_i64 tcg_rd = cpu_reg(s, rd);
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TCGv_i64 tcg_tmp = tcg_temp_new_i64();
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TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
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tcg_gen_andi_i64(tcg_tmp, tcg_rn, 0xffff);
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tcg_gen_bswap16_i64(tcg_rd, tcg_tmp);
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tcg_gen_shri_i64(tcg_tmp, tcg_rn, 16);
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tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff);
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tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
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tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 16, 16);
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if (sf) {
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tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32);
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tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff);
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tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
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tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 32, 16);
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tcg_gen_shri_i64(tcg_tmp, tcg_rn, 48);
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tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
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tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 48, 16);
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}
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tcg_temp_free_i64(tcg_tmp);
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}
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/* C3.5.7 Data-processing (1 source)
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/* C3.5.7 Data-processing (1 source)
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* 31 30 29 28 21 20 16 15 10 9 5 4 0
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* 31 30 29 28 21 20 16 15 10 9 5 4 0
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* +----+---+---+-----------------+---------+--------+------+------+
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* +----+---+---+-----------------+---------+--------+------+------+
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@ -1105,9 +1172,13 @@ static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
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handle_rbit(s, sf, rn, rd);
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handle_rbit(s, sf, rn, rd);
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break;
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break;
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case 1: /* REV16 */
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case 1: /* REV16 */
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handle_rev16(s, sf, rn, rd);
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break;
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case 2: /* REV32 */
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case 2: /* REV32 */
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handle_rev32(s, sf, rn, rd);
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break;
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case 3: /* REV64 */
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case 3: /* REV64 */
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unsupported_encoding(s, insn);
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handle_rev64(s, sf, rn, rd);
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break;
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break;
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case 4: /* CLZ */
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case 4: /* CLZ */
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handle_clz(s, sf, rn, rd);
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handle_clz(s, sf, rn, rd);
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