mirror of https://github.com/proxmox/mirror_qemu
target/arm: Mark up VNCR offsets (offsets 0x168..0x1f8)
Mark up the cpreginfo structs to indicate offsets for system registers from VNCR_EL2, as defined in table D8-66 in rule R_CSRPQ in the Arm ARM. This commit covers offsets 0x168 to 0x1f8. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Miguel Luis <miguel.luis@oracle.com>master
Peter Maydell
parent
bb7b95b070
commit
46932cf26e
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@ -3191,6 +3191,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
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.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
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.type = ARM_CP_IO, .access = PL0_RW,
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.accessfn = gt_ptimer_access,
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.nv2_redirect_offset = 0x180 | NV2_REDIR_NV1,
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.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
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.resetvalue = 0,
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.readfn = gt_phys_redir_ctl_read, .raw_readfn = raw_read,
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@ -3208,6 +3209,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
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.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
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.type = ARM_CP_IO, .access = PL0_RW,
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.accessfn = gt_vtimer_access,
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.nv2_redirect_offset = 0x170 | NV2_REDIR_NV1,
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.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
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.resetvalue = 0,
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.readfn = gt_virt_redir_ctl_read, .raw_readfn = raw_read,
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@ -3287,6 +3289,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
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.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
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.access = PL0_RW,
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.type = ARM_CP_IO,
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.nv2_redirect_offset = 0x178 | NV2_REDIR_NV1,
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.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
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.resetvalue = 0, .accessfn = gt_ptimer_access,
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.readfn = gt_phys_redir_cval_read, .raw_readfn = raw_read,
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@ -3304,6 +3307,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
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.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
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.access = PL0_RW,
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.type = ARM_CP_IO,
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.nv2_redirect_offset = 0x168 | NV2_REDIR_NV1,
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.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
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.resetvalue = 0, .accessfn = gt_vtimer_access,
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.readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read,
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@ -7052,6 +7056,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static const ARMCPRegInfo zcr_reginfo[] = {
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{ .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
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.nv2_redirect_offset = 0x1e0 | NV2_REDIR_NV1,
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.access = PL1_RW, .type = ARM_CP_SVE,
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.fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
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.writefn = zcr_write, .raw_writefn = raw_write },
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@ -7193,6 +7198,7 @@ static const ARMCPRegInfo sme_reginfo[] = {
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.writefn = svcr_write, .raw_writefn = raw_write },
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{ .name = "SMCR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 6,
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.nv2_redirect_offset = 0x1f0 | NV2_REDIR_NV1,
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.access = PL1_RW, .type = ARM_CP_SME,
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.fieldoffset = offsetof(CPUARMState, vfp.smcr_el[1]),
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.writefn = smcr_write, .raw_writefn = raw_write },
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@ -7226,6 +7232,7 @@ static const ARMCPRegInfo sme_reginfo[] = {
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.type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "SMPRIMAP_EL2", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 5,
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.nv2_redirect_offset = 0x1f8,
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.access = PL2_RW, .accessfn = access_smprimap,
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.type = ARM_CP_CONST, .resetvalue = 0 },
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};
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@ -7948,6 +7955,7 @@ static const ARMCPRegInfo mte_reginfo[] = {
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{ .name = "TFSR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 0,
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.access = PL1_RW, .accessfn = access_tfsr_el1,
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.nv2_redirect_offset = 0x190 | NV2_REDIR_NV1,
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.fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[1]) },
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{ .name = "TFSR_EL2", .state = ARM_CP_STATE_AA64,
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.type = ARM_CP_NV2_REDIRECT,
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@ -8122,6 +8130,7 @@ static const ARMCPRegInfo scxtnum_reginfo[] = {
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.opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7,
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.access = PL1_RW, .accessfn = access_scxtnum_el1,
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.fgt = FGT_SCXTNUM_EL1,
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.nv2_redirect_offset = 0x188 | NV2_REDIR_NV1,
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.fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) },
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{ .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7,
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@ -8146,22 +8155,27 @@ static CPAccessResult access_fgt(CPUARMState *env, const ARMCPRegInfo *ri,
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static const ARMCPRegInfo fgt_reginfo[] = {
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{ .name = "HFGRTR_EL2", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
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.nv2_redirect_offset = 0x1b8,
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.access = PL2_RW, .accessfn = access_fgt,
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.fieldoffset = offsetof(CPUARMState, cp15.fgt_read[FGTREG_HFGRTR]) },
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{ .name = "HFGWTR_EL2", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 5,
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.nv2_redirect_offset = 0x1c0,
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.access = PL2_RW, .accessfn = access_fgt,
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.fieldoffset = offsetof(CPUARMState, cp15.fgt_write[FGTREG_HFGWTR]) },
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{ .name = "HDFGRTR_EL2", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 4, .crn = 3, .crm = 1, .opc2 = 4,
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.nv2_redirect_offset = 0x1d0,
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.access = PL2_RW, .accessfn = access_fgt,
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.fieldoffset = offsetof(CPUARMState, cp15.fgt_read[FGTREG_HDFGRTR]) },
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{ .name = "HDFGWTR_EL2", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 4, .crn = 3, .crm = 1, .opc2 = 5,
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.nv2_redirect_offset = 0x1d8,
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.access = PL2_RW, .accessfn = access_fgt,
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.fieldoffset = offsetof(CPUARMState, cp15.fgt_write[FGTREG_HDFGWTR]) },
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{ .name = "HFGITR_EL2", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 6,
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.nv2_redirect_offset = 0x1c8,
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.access = PL2_RW, .accessfn = access_fgt,
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.fieldoffset = offsetof(CPUARMState, cp15.fgt_exec[FGTREG_HFGITR]) },
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};
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@ -8348,12 +8362,14 @@ static const ARMCPRegInfo vhe_reginfo[] = {
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.opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 1,
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.type = ARM_CP_IO | ARM_CP_ALIAS,
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.access = PL2_RW, .accessfn = e2h_access,
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.nv2_redirect_offset = 0x180 | NV2_REDIR_NO_NV1,
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.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
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.writefn = gt_phys_ctl_write, .raw_writefn = raw_write },
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{ .name = "CNTV_CTL_EL02", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 1,
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.type = ARM_CP_IO | ARM_CP_ALIAS,
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.access = PL2_RW, .accessfn = e2h_access,
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.nv2_redirect_offset = 0x170 | NV2_REDIR_NO_NV1,
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.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
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.writefn = gt_virt_ctl_write, .raw_writefn = raw_write },
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{ .name = "CNTP_TVAL_EL02", .state = ARM_CP_STATE_AA64,
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@ -8370,11 +8386,13 @@ static const ARMCPRegInfo vhe_reginfo[] = {
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.opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 2,
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.type = ARM_CP_IO | ARM_CP_ALIAS,
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.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
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.nv2_redirect_offset = 0x178 | NV2_REDIR_NO_NV1,
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.access = PL2_RW, .accessfn = e2h_access,
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.writefn = gt_phys_cval_write, .raw_writefn = raw_write },
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{ .name = "CNTV_CVAL_EL02", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 2,
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.type = ARM_CP_IO | ARM_CP_ALIAS,
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.nv2_redirect_offset = 0x168 | NV2_REDIR_NO_NV1,
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.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
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.access = PL2_RW, .accessfn = e2h_access,
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.writefn = gt_virt_cval_write, .raw_writefn = raw_write },
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