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RISC-V Patches for the 4.0 Soft Freeze, Part 1 

This patch set contains a handful of patches I've collected over the
 last few weeks.  There's nothing really fundamental, but I thought it
 would be good to send these out now as there are some other patch sets
 on the mailing list that are getting ready to go.
 
 As far as the actual patches, there's:
 
 * A set that cleans up our FS dirty-mode handling.
 * Support for writing MISA.
 * The removal of Michael as a maintainer.
 * A fix to {m,s}counteren handling.
 * A fix to make sure the kernel's start address is computed correctly on
   32-bit targets.
 
 This makes my "RISC-V Patches for 3.2, Part 3" pull request defunct, as
 it contains the same patches but based on a newer master.  As usual,
 I've tested this using a Fedora boot on the latest Linux.  This patch
 set does not include Bastian's decodetree patches because there were
 some merge conflicts and while I've cleaned them up I want to get a
 round of review first.
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Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-sf1' into staging

RISC-V Patches for the 4.0 Soft Freeze, Part 1

This patch set contains a handful of patches I've collected over the
last few weeks.  There's nothing really fundamental, but I thought it
would be good to send these out now as there are some other patch sets
on the mailing list that are getting ready to go.

As far as the actual patches, there's:

* A set that cleans up our FS dirty-mode handling.
* Support for writing MISA.
* The removal of Michael as a maintainer.
* A fix to {m,s}counteren handling.
* A fix to make sure the kernel's start address is computed correctly on
  32-bit targets.

This makes my "RISC-V Patches for 3.2, Part 3" pull request defunct, as
it contains the same patches but based on a newer master.  As usual,
I've tested this using a Fedora boot on the latest Linux.  This patch
set does not include Bastian's decodetree patches because there were
some merge conflicts and while I've cleaned them up I want to get a
round of review first.

# gpg: Signature made Wed 13 Feb 2019 15:37:50 GMT
# gpg:                using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
# gpg:                issuer "palmer@dabbelt.com"
# gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown]
# gpg:                 aka "Palmer Dabbelt <palmer@sifive.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41

* remotes/palmer/tags/riscv-for-master-4.0-sf1:
  riscv: Ensure the kernel start address is correctly cast
  target/riscv: fix counter-enable checks in ctr()
  MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer
  RISC-V: Add misa runtime write support
  RISC-V: Add misa.MAFD checks to translate
  RISC-V: Add misa to DisasContext
  RISC-V: Add priv_ver to DisasContext
  RISC-V: Use riscv prefix consistently on cpu helpers
  RISC-V: Implement mstatus.TSR/TW/TVM
  RISC-V: Mark mstatus.fs dirty
  RISC-V: Split out mstatus_fs from tb_flags

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
master
Peter Maydell 2019-02-14 13:15:45 +00:00
parent 190ff53829 40e46e516d
commit 4856c2c70c
14 changed files with 400 additions and 113 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
MAINTAINERS
View File

@ -259,7 +259,6 @@ F: include/hw/ppc/
F: disas/ppc.c
RISC-V
M: Michael Clark <mjc@sifive.com>
M: Palmer Dabbelt <palmer@sifive.com>
M: Alistair Francis <Alistair.Francis@wdc.com>
M: Sagar Karandikar <sagark@eecs.berkeley.edu>

2
hw/riscv/sifive_e.c
View File

@ -74,7 +74,7 @@ static const struct MemmapEntry {
[SIFIVE_E_DTIM] = { 0x80000000, 0x4000 }
};
static uint64_t load_kernel(const char *kernel_filename)
static target_ulong load_kernel(const char *kernel_filename)
{
uint64_t kernel_entry, kernel_high;

2
hw/riscv/sifive_u.c
View File

@ -65,7 +65,7 @@ static const struct MemmapEntry {
#define GEM_REVISION 0x10070109
static uint64_t load_kernel(const char *kernel_filename)
static target_ulong load_kernel(const char *kernel_filename)
{
uint64_t kernel_entry, kernel_high;

2
hw/riscv/spike.c
View File

@ -53,7 +53,7 @@ static const struct MemmapEntry {
[SPIKE_DRAM] = { 0x80000000, 0x0 },
};
static uint64_t load_kernel(const char *kernel_filename)
static target_ulong load_kernel(const char *kernel_filename)
{
uint64_t kernel_entry, kernel_high;

2
hw/riscv/virt.c
View File

@ -62,7 +62,7 @@ static const struct MemmapEntry {
[VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
};
static uint64_t load_kernel(const char *kernel_filename)
static target_ulong load_kernel(const char *kernel_filename)
{
uint64_t kernel_entry, kernel_high;

4
linux-user/riscv/signal.c
View File

@ -83,7 +83,7 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPURISCVState *env)
__put_user(env->fpr[i], &sc->fpr[i]);
}
uint32_t fcsr = csr_read_helper(env, CSR_FCSR); /*riscv_get_fcsr(env);*/
uint32_t fcsr = riscv_csr_read(env, CSR_FCSR);
__put_user(fcsr, &sc->fcsr);
}
@ -159,7 +159,7 @@ static void restore_sigcontext(CPURISCVState *env, struct target_sigcontext *sc)
uint32_t fcsr;
__get_user(fcsr, &sc->fcsr);
csr_write_helper(env, fcsr, CSR_FCSR);
riscv_csr_write(env, CSR_FCSR, fcsr);
}
static void restore_ucontext(CPURISCVState *env, struct target_ucontext *uc)

2
target/riscv/cpu.c
View File

@ -88,7 +88,7 @@ typedef struct RISCVCPUInfo {
static void set_misa(CPURISCVState *env, target_ulong misa)
{
env->misa = misa;
env->misa_mask = env->misa = misa;
}
static void set_versions(CPURISCVState *env, int user_ver, int priv_ver)

31
target/riscv/cpu.h
View File

@ -86,7 +86,8 @@
so a cpu features bitfield is required, likewise for optional PMP support */
enum {
RISCV_FEATURE_MMU,
RISCV_FEATURE_PMP
RISCV_FEATURE_PMP,
RISCV_FEATURE_MISA
};
#define USER_VERSION_2_02_0 0x00020200
@ -118,6 +119,7 @@ struct CPURISCVState {
target_ulong user_ver;
target_ulong priv_ver;
target_ulong misa;
target_ulong misa_mask;
uint32_t features;
@ -256,7 +258,7 @@ int riscv_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size,
char *riscv_isa_string(RISCVCPU *cpu);
void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
#define cpu_signal_handler cpu_riscv_signal_handler
#define cpu_signal_handler riscv_cpu_signal_handler
#define cpu_list riscv_cpu_list
#define cpu_mmu_index riscv_cpu_mmu_index
@ -264,19 +266,18 @@ void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
#endif
void riscv_set_mode(CPURISCVState *env, target_ulong newpriv);
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
void riscv_translate_init(void);
RISCVCPU *cpu_riscv_init(const char *cpu_model);
int cpu_riscv_signal_handler(int host_signum, void *pinfo, void *puc);
void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
uint32_t exception, uintptr_t pc);
int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
uint32_t exception, uintptr_t pc);
target_ulong cpu_riscv_get_fflags(CPURISCVState *env);
void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong);
target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
#define TB_FLAGS_MMU_MASK 3
#define TB_FLAGS_FP_ENABLE MSTATUS_FS
#define TB_FLAGS_MMU_MASK 3
#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *flags)
@ -284,7 +285,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
*pc = env->pc;
*cs_base = 0;
#ifdef CONFIG_USER_ONLY
*flags = TB_FLAGS_FP_ENABLE;
*flags = TB_FLAGS_MSTATUS_FS;
#else
*flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS);
#endif
@ -293,13 +294,13 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask);
static inline void csr_write_helper(CPURISCVState *env, target_ulong val,
int csrno)
static inline void riscv_csr_write(CPURISCVState *env, int csrno,
target_ulong val)
{
riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
}
static inline target_ulong csr_read_helper(CPURISCVState *env, int csrno)
static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
{
target_ulong val = 0;
riscv_csrrw(env, csrno, &val, 0, 0);

11
target/riscv/cpu_bits.h
View File

@ -311,10 +311,21 @@
#define MSTATUS32_SD 0x80000000
#define MSTATUS64_SD 0x8000000000000000ULL
#define MISA32_MXL 0xC0000000
#define MISA64_MXL 0xC000000000000000ULL
#define MXL_RV32 1
#define MXL_RV64 2
#define MXL_RV128 3
#if defined(TARGET_RISCV32)
#define MSTATUS_SD MSTATUS32_SD
#define MISA_MXL MISA32_MXL
#define MXL_VAL MXL_RV32
#elif defined(TARGET_RISCV64)
#define MSTATUS_SD MSTATUS64_SD
#define MISA_MXL MISA64_MXL
#define MXL_VAL MXL_RV64
#endif
/* sstatus CSR bits */

10
target/riscv/cpu_helper.c
View File

@ -93,7 +93,7 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
return old;
}
void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
{
if (newpriv > PRV_M) {
g_assert_not_reached();
@ -366,7 +366,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
g_assert_not_reached();
}
env->badaddr = addr;
do_raise_exception_err(env, cs->exception_index, retaddr);
riscv_raise_exception(env, cs->exception_index, retaddr);
}
/* called by qemu's softmmu to fill the qemu tlb */
@ -378,7 +378,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size,
if (ret == TRANSLATE_FAIL) {
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
do_raise_exception_err(env, cs->exception_index, retaddr);
riscv_raise_exception(env, cs->exception_index, retaddr);
}
}
@ -530,7 +530,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
s = set_field(s, MSTATUS_SPP, env->priv);
s = set_field(s, MSTATUS_SIE, 0);
env->mstatus = s;
riscv_set_mode(env, PRV_S);
riscv_cpu_set_mode(env, PRV_S);
} else {
/* No need to check MTVEC for misaligned - lower 2 bits cannot be set */
env->pc = env->mtvec;
@ -555,7 +555,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
s = set_field(s, MSTATUS_MPP, env->priv);
s = set_field(s, MSTATUS_MIE, 0);
env->mstatus = s;
riscv_set_mode(env, PRV_M);
riscv_cpu_set_mode(env, PRV_M);
}
/* TODO yield load reservation */
#endif

103
target/riscv/csr.c
View File

@ -56,9 +56,15 @@ static int fs(CPURISCVState *env, int csrno)
static int ctr(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
target_ulong ctr_en = env->priv == PRV_U ? env->scounteren :
env->priv == PRV_S ? env->mcounteren : -1U;
if (!(ctr_en & (1 << (csrno & 31)))) {
uint32_t ctr_en = ~0u;
if (env->priv < PRV_M) {
ctr_en &= env->mcounteren;
}
if (env->priv < PRV_S) {
ctr_en &= env->scounteren;
}
if (!(ctr_en & (1u << (csrno & 31)))) {
return -1;
}
#endif
@ -90,7 +96,7 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
return -1;
}
#endif
*val = cpu_riscv_get_fflags(env);
*val = riscv_cpu_get_fflags(env);
return 0;
}
@ -102,7 +108,7 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
}
env->mstatus |= MSTATUS_FS;
#endif
cpu_riscv_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
return 0;
}
@ -136,7 +142,7 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
return -1;
}
#endif
*val = (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT)
*val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
| (env->frm << FSR_RD_SHIFT);
return 0;
}
@ -150,7 +156,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
env->mstatus |= MSTATUS_FS;
#endif
env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
cpu_riscv_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
return 0;
}
@ -305,7 +311,8 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
}
mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
MSTATUS_MPP | MSTATUS_MXR;
MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
MSTATUS_TW;
}
/* silenty discard mstatus.mpp writes for unsupported modes */
@ -317,18 +324,6 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
mstatus = (mstatus & ~mask) | (val & mask);
/* Note: this is a workaround for an issue where mstatus.FS
does not report dirty after floating point operations
that modify floating point state. This workaround is
technically compliant with the RISC-V Privileged
specification as it is legal to return only off, or dirty.
at the expense of extra floating point save/restore. */
/* FP is always dirty or off */
if (mstatus & MSTATUS_FS) {
mstatus |= MSTATUS_FS;
}
int dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
((mstatus & MSTATUS_XS) == MSTATUS_XS);
mstatus = set_field(mstatus, MSTATUS_SD, dirty);
@ -343,6 +338,58 @@ static int read_misa(CPURISCVState *env, int csrno, target_ulong *val)
return 0;
}
static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
{
if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
/* drop write to misa */
return 0;
}
/* 'I' or 'E' must be present */
if (!(val & (RVI | RVE))) {
/* It is not, drop write to misa */
return 0;
}
/* 'E' excludes all other extensions */
if (val & RVE) {
/* when we support 'E' we can do "val = RVE;" however
* for now we just drop writes if 'E' is present.
*/
return 0;
}
/* Mask extensions that are not supported by this hart */
val &= env->misa_mask;
/* Mask extensions that are not supported by QEMU */
val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
/* 'D' depends on 'F', so clear 'D' if 'F' is not present */
if ((val & RVD) && !(val & RVF)) {
val &= ~RVD;
}
/* Suppress 'C' if next instruction is not aligned
* TODO: this should check next_pc
*/
if ((val & RVC) && (GETPC() & ~3) != 0) {
val &= ~RVC;
}
/* misa.MXL writes are not supported by QEMU */
val = (env->misa & MISA_MXL) | (val & ~MISA_MXL);
/* flush translation cache */
if (val != env->misa) {
tb_flush(CPU(riscv_env_get_cpu(env)));
}
env->misa = val;
return 0;
}
static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->medeleg;
@ -654,7 +701,11 @@ static int read_satp(CPURISCVState *env, int csrno, target_ulong *val)
if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
*val = 0;
} else if (env->priv_ver >= PRIV_VERSION_1_10_0) {
*val = env->satp;
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
return -1;
} else {
*val = env->satp;
}
} else {
*val = env->sptbr;
}
@ -675,8 +726,12 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
validate_vm(env, get_field(val, SATP_MODE)) &&
((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
{
tlb_flush(CPU(riscv_env_get_cpu(env)));
env->satp = val;
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
return -1;
} else {
tlb_flush(CPU(riscv_env_get_cpu(env)));
env->satp = val;
}
}
return 0;
}
@ -813,7 +868,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* Machine Trap Setup */
[CSR_MSTATUS] = { any, read_mstatus, write_mstatus },
[CSR_MISA] = { any, read_misa },
[CSR_MISA] = { any, read_misa, write_misa },
[CSR_MIDELEG] = { any, read_mideleg, write_mideleg },
[CSR_MEDELEG] = { any, read_medeleg, write_medeleg },
[CSR_MIE] = { any, read_mie, write_mie },

6
target/riscv/fpu_helper.c
View File

@ -22,7 +22,7 @@
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
target_ulong cpu_riscv_get_fflags(CPURISCVState *env)
target_ulong riscv_cpu_get_fflags(CPURISCVState *env)
{
int soft = get_float_exception_flags(&env->fp_status);
target_ulong hard = 0;
@ -36,7 +36,7 @@ target_ulong cpu_riscv_get_fflags(CPURISCVState *env)
return hard;
}
void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong hard)
void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard)
{
int soft = 0;
@ -73,7 +73,7 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm)
softrm = float_round_ties_away;
break;
default:
do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
set_float_rounding_mode(softrm, &env->fp_status);

47
target/riscv/op_helper.c
View File

@ -25,7 +25,7 @@
#include "exec/helper-proto.h"
/* Exceptions processing helpers */
void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
uint32_t exception, uintptr_t pc)
{
CPUState *cs = CPU(riscv_env_get_cpu(env));
@ -36,7 +36,7 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
void helper_raise_exception(CPURISCVState *env, uint32_t exception)
{
do_raise_exception_err(env, exception, 0);
riscv_raise_exception(env, exception, 0);
}
target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
@ -44,7 +44,7 @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
{
target_ulong val = 0;
if (riscv_csrrw(env, csr, &val, src, -1) < 0) {
do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
return val;
}
@ -54,7 +54,7 @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
{
target_ulong val = 0;
if (riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0) < 0) {
do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
return val;
}
@ -64,7 +64,7 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
{
target_ulong val = 0;
if (riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0) < 0) {
do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
return val;
}
@ -74,12 +74,17 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
{
if (!(env->priv >= PRV_S)) {
do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
target_ulong retpc = env->sepc;
if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
}
if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
get_field(env->mstatus, MSTATUS_TSR)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
target_ulong mstatus = env->mstatus;
@ -90,7 +95,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
get_field(mstatus, MSTATUS_SPIE));
mstatus = set_field(mstatus, MSTATUS_SPIE, 0);
mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
riscv_set_mode(env, prev_priv);
riscv_cpu_set_mode(env, prev_priv);
env->mstatus = mstatus;
return retpc;
@ -99,12 +104,12 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
{
if (!(env->priv >= PRV_M)) {
do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
target_ulong retpc = env->mepc;
if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
}
target_ulong mstatus = env->mstatus;
@ -115,7 +120,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
get_field(mstatus, MSTATUS_MPIE));
mstatus = set_field(mstatus, MSTATUS_MPIE, 0);
mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
riscv_set_mode(env, prev_priv);
riscv_cpu_set_mode(env, prev_priv);
env->mstatus = mstatus;
return retpc;
@ -125,16 +130,28 @@ void helper_wfi(CPURISCVState *env)
{
CPUState *cs = CPU(riscv_env_get_cpu(env));
cs->halted = 1;
cs->exception_index = EXCP_HLT;
cpu_loop_exit(cs);
if (env->priv == PRV_S &&
env->priv_ver >= PRIV_VERSION_1_10_0 &&
get_field(env->mstatus, MSTATUS_TW)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
} else {
cs->halted = 1;
cs->exception_index = EXCP_HLT;
cpu_loop_exit(cs);
}
}
void helper_tlb_flush(CPURISCVState *env)
{
RISCVCPU *cpu = riscv_env_get_cpu(env);
CPUState *cs = CPU(cpu);
tlb_flush(cs);
if (env->priv == PRV_S &&
env->priv_ver >= PRIV_VERSION_1_10_0 &&
get_field(env->mstatus, MSTATUS_TVM)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
} else {
tlb_flush(cs);
}
}
#endif /* !CONFIG_USER_ONLY */

290
target/riscv/translate.c
View File

@ -43,8 +43,10 @@ typedef struct DisasContext {
DisasContextBase base;
/* pc_succ_insn points to the instruction following base.pc_next */
target_ulong pc_succ_insn;
target_ulong priv_ver;
uint32_t opcode;
uint32_t flags;
uint32_t mstatus_fs;
uint32_t misa;
uint32_t mem_idx;
/* Remember the rounding mode encoded in the previous fp instruction,
which we have already installed into env->fp_status. Or -1 for
@ -74,6 +76,11 @@ static const int tcg_memop_lookup[8] = {
#define CASE_OP_32_64(X) case X
#endif
static inline bool has_ext(DisasContext *ctx, uint32_t ext)
{
return ctx->misa & ext;
}
static void generate_exception(DisasContext *ctx, int excp)
{
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
@ -284,24 +291,42 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
tcg_gen_and_tl(source1, source1, source2);
break;
CASE_OP_32_64(OPC_RISC_MUL):
if (!has_ext(ctx, RVM)) {
goto do_illegal;
}
tcg_gen_mul_tl(source1, source1, source2);
break;
case OPC_RISC_MULH:
if (!has_ext(ctx, RVM)) {
goto do_illegal;
}
tcg_gen_muls2_tl(source2, source1, source1, source2);
break;
case OPC_RISC_MULHSU:
if (!has_ext(ctx, RVM)) {
goto do_illegal;
}
gen_mulhsu(source1, source1, source2);
break;
case OPC_RISC_MULHU:
if (!has_ext(ctx, RVM)) {
goto do_illegal;
}
tcg_gen_mulu2_tl(source2, source1, source1, source2);
break;
#if defined(TARGET_RISCV64)
case OPC_RISC_DIVW:
if (!has_ext(ctx, RVM)) {
goto do_illegal;
}
tcg_gen_ext32s_tl(source1, source1);
tcg_gen_ext32s_tl(source2, source2);
/* fall through to DIV */
#endif
case OPC_RISC_DIV:
if (!has_ext(ctx, RVM)) {
goto do_illegal;
}
/* Handle by altering args to tcg_gen_div to produce req'd results:
* For overflow: want source1 in source1 and 1 in source2
* For div by zero: want -1 in source1 and 1 in source2 -> -1 result */
@ -333,11 +358,17 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
break;
#if defined(TARGET_RISCV64)
case OPC_RISC_DIVUW:
if (!has_ext(ctx, RVM)) {
goto do_illegal;
}
tcg_gen_ext32u_tl(source1, source1);
tcg_gen_ext32u_tl(source2, source2);
/* fall through to DIVU */
#endif
case OPC_RISC_DIVU:
if (!has_ext(ctx, RVM)) {
goto do_illegal;
}
cond1 = tcg_temp_new();
zeroreg = tcg_const_tl(0);
resultopt1 = tcg_temp_new();
@ -357,11 +388,17 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
break;
#if defined(TARGET_RISCV64)
case OPC_RISC_REMW:
if (!has_ext(ctx, RVM)) {
goto do_illegal;
}
tcg_gen_ext32s_tl(source1, source1);
tcg_gen_ext32s_tl(source2, source2);
/* fall through to REM */
#endif
case OPC_RISC_REM:
if (!has_ext(ctx, RVM)) {
goto do_illegal;
}
cond1 = tcg_temp_new();
cond2 = tcg_temp_new();
zeroreg = tcg_const_tl(0);
@ -389,11 +426,17 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
break;
#if defined(TARGET_RISCV64)
case OPC_RISC_REMUW:
if (!has_ext(ctx, RVM)) {
goto do_illegal;
}
tcg_gen_ext32u_tl(source1, source1);
tcg_gen_ext32u_tl(source2, source2);
/* fall through to REMU */
#endif
case OPC_RISC_REMU:
if (!has_ext(ctx, RVM)) {
goto do_illegal;
}
cond1 = tcg_temp_new();
zeroreg = tcg_const_tl(0);
resultopt1 = tcg_temp_new();
@ -411,6 +454,7 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
tcg_temp_free(zeroreg);
tcg_temp_free(resultopt1);
break;
do_illegal:
default:
gen_exception_illegal(ctx);
return;
@ -505,14 +549,13 @@ static void gen_arith_imm(DisasContext *ctx, uint32_t opc, int rd,
tcg_temp_free(source1);
}
static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
target_ulong imm)
static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
{
target_ulong next_pc;
/* check misaligned: */
next_pc = ctx->base.pc_next + imm;
if (!riscv_has_ext(env, RVC)) {
if (!has_ext(ctx, RVC)) {
if ((next_pc & 0x3) != 0) {
gen_exception_inst_addr_mis(ctx);
return;
@ -526,8 +569,8 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
ctx->base.is_jmp = DISAS_NORETURN;
}
static void gen_jalr(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
int rd, int rs1, target_long imm)
static void gen_jalr(DisasContext *ctx, uint32_t opc, int rd, int rs1,
target_long imm)
{
/* no chaining with JALR */
TCGLabel *misaligned = NULL;
@ -539,7 +582,7 @@ static void gen_jalr(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
tcg_gen_addi_tl(cpu_pc, cpu_pc, imm);
tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
if (!riscv_has_ext(env, RVC)) {
if (!has_ext(ctx, RVC)) {
misaligned = gen_new_label();
tcg_gen_andi_tl(t0, cpu_pc, 0x2);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
@ -564,8 +607,8 @@ static void gen_jalr(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
tcg_temp_free(t0);
}
static void gen_branch(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
int rs1, int rs2, target_long bimm)
static void gen_branch(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
target_long bimm)
{
TCGLabel *l = gen_new_label();
TCGv source1, source2;
@ -602,7 +645,7 @@ static void gen_branch(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
gen_set_label(l); /* branch taken */
if (!riscv_has_ext(env, RVC) && ((ctx->base.pc_next + bimm) & 0x3)) {
if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + bimm) & 0x3)) {
/* misaligned */
gen_exception_inst_addr_mis(ctx);
} else {
@ -651,12 +694,37 @@ static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
tcg_temp_free(dat);
}
#ifndef CONFIG_USER_ONLY
/* The states of mstatus_fs are:
* 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
* We will have already diagnosed disabled state,
* and need to turn initial/clean into dirty.
*/
static void mark_fs_dirty(DisasContext *ctx)
{
TCGv tmp;
if (ctx->mstatus_fs == MSTATUS_FS) {
return;
}
/* Remember the state change for the rest of the TB. */
ctx->mstatus_fs = MSTATUS_FS;
tmp = tcg_temp_new();
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
tcg_temp_free(tmp);
}
#else
static inline void mark_fs_dirty(DisasContext *ctx) { }
#endif
static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
int rs1, target_long imm)
{
TCGv t0;
if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
if (ctx->mstatus_fs == 0) {
gen_exception_illegal(ctx);
return;
}
@ -667,18 +735,27 @@ static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
switch (opc) {
case OPC_RISC_FLW:
if (!has_ext(ctx, RVF)) {
goto do_illegal;
}
tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
/* RISC-V requires NaN-boxing of narrower width floating point values */
tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
break;
case OPC_RISC_FLD:
if (!has_ext(ctx, RVD)) {
goto do_illegal;
}
tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
break;
do_illegal:
default:
gen_exception_illegal(ctx);
break;
}
tcg_temp_free(t0);
mark_fs_dirty(ctx);
}
static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
@ -686,7 +763,7 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
{
TCGv t0;
if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
if (ctx->mstatus_fs == 0) {
gen_exception_illegal(ctx);
return;
}
@ -697,11 +774,18 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
switch (opc) {
case OPC_RISC_FSW:
if (!has_ext(ctx, RVF)) {
goto do_illegal;
}
tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
break;
case OPC_RISC_FSD:
if (!has_ext(ctx, RVD)) {
goto do_illegal;
}
tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
break;
do_illegal:
default:
gen_exception_illegal(ctx);
break;
@ -865,15 +949,22 @@ static void gen_fp_fmadd(DisasContext *ctx, uint32_t opc, int rd,
{
switch (opc) {
case OPC_RISC_FMADD_S:
if (!has_ext(ctx, RVF)) {
goto do_illegal;
}
gen_set_rm(ctx, rm);
gen_helper_fmadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
cpu_fpr[rs2], cpu_fpr[rs3]);
break;
case OPC_RISC_FMADD_D:
if (!has_ext(ctx, RVD)) {
goto do_illegal;
}
gen_set_rm(ctx, rm);
gen_helper_fmadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
cpu_fpr[rs2], cpu_fpr[rs3]);
break;
do_illegal:
default:
gen_exception_illegal(ctx);
break;
@ -885,15 +976,22 @@ static void gen_fp_fmsub(DisasContext *ctx, uint32_t opc, int rd,
{
switch (opc) {
case OPC_RISC_FMSUB_S:
if (!has_ext(ctx, RVF)) {
goto do_illegal;
}
gen_set_rm(ctx, rm);
gen_helper_fmsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
cpu_fpr[rs2], cpu_fpr[rs3]);
break;
case OPC_RISC_FMSUB_D:
if (!has_ext(ctx, RVD)) {
goto do_illegal;
}
gen_set_rm(ctx, rm);
gen_helper_fmsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
cpu_fpr[rs2], cpu_fpr[rs3]);
break;
do_illegal:
default:
gen_exception_illegal(ctx);
break;
@ -905,15 +1003,22 @@ static void gen_fp_fnmsub(DisasContext *ctx, uint32_t opc, int rd,
{
switch (opc) {
case OPC_RISC_FNMSUB_S:
if (!has_ext(ctx, RVF)) {
goto do_illegal;
}
gen_set_rm(ctx, rm);
gen_helper_fnmsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
cpu_fpr[rs2], cpu_fpr[rs3]);
break;
case OPC_RISC_FNMSUB_D:
if (!has_ext(ctx, RVD)) {
goto do_illegal;
}
gen_set_rm(ctx, rm);
gen_helper_fnmsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
cpu_fpr[rs2], cpu_fpr[rs3]);
break;
do_illegal:
default:
gen_exception_illegal(ctx);
break;
@ -925,15 +1030,22 @@ static void gen_fp_fnmadd(DisasContext *ctx, uint32_t opc, int rd,
{
switch (opc) {
case OPC_RISC_FNMADD_S:
if (!has_ext(ctx, RVF)) {
goto do_illegal;
}
gen_set_rm(ctx, rm);
gen_helper_fnmadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
cpu_fpr[rs2], cpu_fpr[rs3]);
break;
case OPC_RISC_FNMADD_D:
if (!has_ext(ctx, RVD)) {
goto do_illegal;
}
gen_set_rm(ctx, rm);
gen_helper_fnmadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
cpu_fpr[rs2], cpu_fpr[rs3]);
break;
do_illegal:
default:
gen_exception_illegal(ctx);
break;
@ -944,37 +1056,59 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
int rs1, int rs2, int rm)
{
TCGv t0 = NULL;
bool fp_output = true;
if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
if (ctx->mstatus_fs == 0) {
goto do_illegal;
}
switch (opc) {
case OPC_RISC_FADD_S:
if (!has_ext(ctx, RVF)) {
goto do_illegal;
}
gen_set_rm(ctx, rm);
gen_helper_fadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case OPC_RISC_FSUB_S:
if (!has_ext(ctx, RVF)) {
goto do_illegal;
}
gen_set_rm(ctx, rm);
gen_helper_fsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case OPC_RISC_FMUL_S:
if (!has_ext(ctx, RVF)) {
goto do_illegal;
}
gen_set_rm(ctx, rm);
gen_helper_fmul_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case OPC_RISC_FDIV_S:
if (!has_ext(ctx, RVF)) {
goto do_illegal;
}
gen_set_rm(ctx, rm);
gen_helper_fdiv_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case OPC_RISC_FSQRT_S:
if (!has_ext(ctx, RVF)) {
goto do_illegal;
}
gen_set_rm(ctx, rm);
gen_helper_fsqrt_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
break;
case OPC_RISC_FSGNJ_S:
if (!has_ext(ctx, RVF)) {
goto do_illegal;
}
gen_fsgnj(ctx, rd, rs1, rs2, rm, INT32_MIN);
break;
case OPC_RISC_FMIN_S:
if (!has_ext(ctx, RVF)) {
goto do_illegal;
}
/* also handles: OPC_RISC_FMAX_S */
switch (rm) {
case 0x0:
@ -990,6 +1124,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
case OPC_RISC_FEQ_S:
/* also handles: OPC_RISC_FLT_S, OPC_RISC_FLE_S */
if (!has_ext(ctx, RVF)) {
goto do_illegal;
}
t0 = tcg_temp_new();
switch (rm) {
case 0x0:
@ -1006,10 +1143,14 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
}
gen_set_gpr(rd, t0);
tcg_temp_free(t0);
fp_output = false;
break;
case OPC_RISC_FCVT_W_S:
/* also OPC_RISC_FCVT_WU_S, OPC_RISC_FCVT_L_S, OPC_RISC_FCVT_LU_S */
if (!has_ext(ctx, RVF)) {
goto do_illegal;
}
t0 = tcg_temp_new();
switch (rs2) {
case 0: /* FCVT_W_S */
@ -1035,10 +1176,14 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
}
gen_set_gpr(rd, t0);
tcg_temp_free(t0);
fp_output = false;
break;
case OPC_RISC_FCVT_S_W:
/* also OPC_RISC_FCVT_S_WU, OPC_RISC_FCVT_S_L, OPC_RISC_FCVT_S_LU */
if (!has_ext(ctx, RVF)) {
goto do_illegal;
}
t0 = tcg_temp_new();
gen_get_gpr(t0, rs1);
switch (rs2) {
@ -1068,6 +1213,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
case OPC_RISC_FMV_X_S:
/* also OPC_RISC_FCLASS_S */
if (!has_ext(ctx, RVF)) {
goto do_illegal;
}
t0 = tcg_temp_new();
switch (rm) {
case 0: /* FMV */
@ -1085,9 +1233,13 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
}
gen_set_gpr(rd, t0);
tcg_temp_free(t0);
fp_output = false;
break;
case OPC_RISC_FMV_S_X:
if (!has_ext(ctx, RVF)) {
goto do_illegal;
}
t0 = tcg_temp_new();
gen_get_gpr(t0, rs1);
#if defined(TARGET_RISCV64)
@ -1100,22 +1252,37 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
/* double */
case OPC_RISC_FADD_D:
if (!has_ext(ctx, RVD)) {
goto do_illegal;
}
gen_set_rm(ctx, rm);
gen_helper_fadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case OPC_RISC_FSUB_D:
if (!has_ext(ctx, RVD)) {
goto do_illegal;
}
gen_set_rm(ctx, rm);
gen_helper_fsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case OPC_RISC_FMUL_D:
if (!has_ext(ctx, RVD)) {
goto do_illegal;
}
gen_set_rm(ctx, rm);
gen_helper_fmul_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case OPC_RISC_FDIV_D:
if (!has_ext(ctx, RVD)) {
goto do_illegal;
}
gen_set_rm(ctx, rm);
gen_helper_fdiv_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case OPC_RISC_FSQRT_D:
if (!has_ext(ctx, RVD)) {
goto do_illegal;
}
gen_set_rm(ctx, rm);
gen_helper_fsqrt_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
break;
@ -1125,6 +1292,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
case OPC_RISC_FMIN_D:
/* also OPC_RISC_FMAX_D */
if (!has_ext(ctx, RVD)) {
goto do_illegal;
}
switch (rm) {
case 0:
gen_helper_fmin_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
@ -1138,6 +1308,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
break;
case OPC_RISC_FCVT_S_D:
if (!has_ext(ctx, RVD)) {
goto do_illegal;
}
switch (rs2) {
case 1:
gen_set_rm(ctx, rm);
@ -1149,6 +1322,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
break;
case OPC_RISC_FCVT_D_S:
if (!has_ext(ctx, RVD)) {
goto do_illegal;
}
switch (rs2) {
case 0:
gen_set_rm(ctx, rm);
@ -1161,6 +1337,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
case OPC_RISC_FEQ_D:
/* also OPC_RISC_FLT_D, OPC_RISC_FLE_D */
if (!has_ext(ctx, RVD)) {
goto do_illegal;
}
t0 = tcg_temp_new();
switch (rm) {
case 0:
@ -1177,10 +1356,14 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
}
gen_set_gpr(rd, t0);
tcg_temp_free(t0);
fp_output = false;
break;
case OPC_RISC_FCVT_W_D:
/* also OPC_RISC_FCVT_WU_D, OPC_RISC_FCVT_L_D, OPC_RISC_FCVT_LU_D */
if (!has_ext(ctx, RVD)) {
goto do_illegal;
}
t0 = tcg_temp_new();
switch (rs2) {
case 0:
@ -1206,10 +1389,14 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
}
gen_set_gpr(rd, t0);
tcg_temp_free(t0);
fp_output = false;
break;
case OPC_RISC_FCVT_D_W:
/* also OPC_RISC_FCVT_D_WU, OPC_RISC_FCVT_D_L, OPC_RISC_FCVT_D_LU */
if (!has_ext(ctx, RVD)) {
goto do_illegal;
}
t0 = tcg_temp_new();
gen_get_gpr(t0, rs1);
switch (rs2) {
@ -1239,6 +1426,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
case OPC_RISC_FMV_X_D:
/* also OPC_RISC_FCLASS_D */
if (!has_ext(ctx, RVD)) {
goto do_illegal;
}
switch (rm) {
#if defined(TARGET_RISCV64)
case 0: /* FMV */
@ -1254,10 +1444,14 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
default:
goto do_illegal;
}
fp_output = false;
break;
#if defined(TARGET_RISCV64)
case OPC_RISC_FMV_D_X:
if (!has_ext(ctx, RVD)) {
goto do_illegal;
}
t0 = tcg_temp_new();
gen_get_gpr(t0, rs1);
tcg_gen_mov_tl(cpu_fpr[rd], t0);
@ -1271,12 +1465,16 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
tcg_temp_free(t0);
}
gen_exception_illegal(ctx);
break;
return;
}
if (fp_output) {
mark_fs_dirty(ctx);
}
}
static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
int rd, int rs1, int csr)
static void gen_system(DisasContext *ctx, uint32_t opc, int rd, int rs1,
int csr)
{
TCGv source1, csr_store, dest, rs1_pass, imm_rs1;
source1 = tcg_temp_new();
@ -1292,7 +1490,7 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
#ifndef CONFIG_USER_ONLY
/* Extract funct7 value and check whether it matches SFENCE.VMA */
if ((opc == OPC_RISC_ECALL) && ((csr >> 5) == 9)) {
if (env->priv_ver == PRIV_VERSION_1_10_0) {
if (ctx->priv_ver == PRIV_VERSION_1_10_0) {
/* sfence.vma */
/* TODO: handle ASID specific fences */
gen_helper_tlb_flush(cpu_env);
@ -1322,7 +1520,7 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
gen_exception_illegal(ctx);
break;
case 0x102: /* SRET */
if (riscv_has_ext(env, RVS)) {
if (has_ext(ctx, RVS)) {
gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
tcg_gen_exit_tb(NULL, 0); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
@ -1346,7 +1544,7 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
gen_helper_wfi(cpu_env);
break;
case 0x104: /* SFENCE.VM */
if (env->priv_ver <= PRIV_VERSION_1_09_1) {
if (ctx->priv_ver <= PRIV_VERSION_1_09_1) {
gen_helper_tlb_flush(cpu_env);
} else {
gen_exception_illegal(ctx);
@ -1467,7 +1665,7 @@ static void decode_RV32_64C0(DisasContext *ctx)
}
}
static void decode_RV32_64C1(CPURISCVState *env, DisasContext *ctx)
static void decode_RV32_64C1(DisasContext *ctx)
{
uint8_t funct3 = extract32(ctx->opcode, 13, 3);
uint8_t rd_rs1 = GET_C_RS1(ctx->opcode);
@ -1487,7 +1685,7 @@ static void decode_RV32_64C1(CPURISCVState *env, DisasContext *ctx)
GET_C_IMM(ctx->opcode));
#else
/* C.JAL(RV32) -> jal x1, offset[11:1] */
gen_jal(env, ctx, 1, GET_C_J_IMM(ctx->opcode));
gen_jal(ctx, 1, GET_C_J_IMM(ctx->opcode));
#endif
break;
case 2:
@ -1566,22 +1764,22 @@ static void decode_RV32_64C1(CPURISCVState *env, DisasContext *ctx)
break;
case 5:
/* C.J -> jal x0, offset[11:1]*/
gen_jal(env, ctx, 0, GET_C_J_IMM(ctx->opcode));
gen_jal(ctx, 0, GET_C_J_IMM(ctx->opcode));
break;
case 6:
/* C.BEQZ -> beq rs1', x0, offset[8:1]*/
rs1s = GET_C_RS1S(ctx->opcode);
gen_branch(env, ctx, OPC_RISC_BEQ, rs1s, 0, GET_C_B_IMM(ctx->opcode));
gen_branch(ctx, OPC_RISC_BEQ, rs1s, 0, GET_C_B_IMM(ctx->opcode));
break;
case 7:
/* C.BNEZ -> bne rs1', x0, offset[8:1]*/
rs1s = GET_C_RS1S(ctx->opcode);
gen_branch(env, ctx, OPC_RISC_BNE, rs1s, 0, GET_C_B_IMM(ctx->opcode));
gen_branch(ctx, OPC_RISC_BNE, rs1s, 0, GET_C_B_IMM(ctx->opcode));
break;
}
}
static void decode_RV32_64C2(CPURISCVState *env, DisasContext *ctx)
static void decode_RV32_64C2(DisasContext *ctx)
{
uint8_t rd, rs2;
uint8_t funct3 = extract32(ctx->opcode, 13, 3);
@ -1615,7 +1813,7 @@ static void decode_RV32_64C2(CPURISCVState *env, DisasContext *ctx)
if (extract32(ctx->opcode, 12, 1) == 0) {
if (rs2 == 0) {
/* C.JR -> jalr x0, rs1, 0*/
gen_jalr(env, ctx, OPC_RISC_JALR, 0, rd, 0);
gen_jalr(ctx, OPC_RISC_JALR, 0, rd, 0);
} else {
/* C.MV -> add rd, x0, rs2 */
gen_arith(ctx, OPC_RISC_ADD, rd, 0, rs2);
@ -1623,11 +1821,11 @@ static void decode_RV32_64C2(CPURISCVState *env, DisasContext *ctx)
} else {
if (rd == 0) {
/* C.EBREAK -> ebreak*/
gen_system(env, ctx, OPC_RISC_ECALL, 0, 0, 0x1);
gen_system(ctx, OPC_RISC_ECALL, 0, 0, 0x1);
} else {
if (rs2 == 0) {
/* C.JALR -> jalr x1, rs1, 0*/
gen_jalr(env, ctx, OPC_RISC_JALR, 1, rd, 0);
gen_jalr(ctx, OPC_RISC_JALR, 1, rd, 0);
} else {
/* C.ADD -> add rd, rd, rs2 */
gen_arith(ctx, OPC_RISC_ADD, rd, rd, rs2);
@ -1659,7 +1857,7 @@ static void decode_RV32_64C2(CPURISCVState *env, DisasContext *ctx)
}
}
static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
static void decode_RV32_64C(DisasContext *ctx)
{
uint8_t op = extract32(ctx->opcode, 0, 2);
@ -1668,15 +1866,15 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
decode_RV32_64C0(ctx);
break;
case 1:
decode_RV32_64C1(env, ctx);
decode_RV32_64C1(ctx);
break;
case 2:
decode_RV32_64C2(env, ctx);
decode_RV32_64C2(ctx);
break;
}
}
static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
static void decode_RV32_64G(DisasContext *ctx)
{
int rs1;
int rs2;
@ -1711,13 +1909,13 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
break;
case OPC_RISC_JAL:
imm = GET_JAL_IMM(ctx->opcode);
gen_jal(env, ctx, rd, imm);
gen_jal(ctx, rd, imm);
break;
case OPC_RISC_JALR:
gen_jalr(env, ctx, MASK_OP_JALR(ctx->opcode), rd, rs1, imm);
gen_jalr(ctx, MASK_OP_JALR(ctx->opcode), rd, rs1, imm);
break;
case OPC_RISC_BRANCH:
gen_branch(env, ctx, MASK_OP_BRANCH(ctx->opcode), rs1, rs2,
gen_branch(ctx, MASK_OP_BRANCH(ctx->opcode), rs1, rs2,
GET_B_IMM(ctx->opcode));
break;
case OPC_RISC_LOAD:
@ -1753,6 +1951,9 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
GET_STORE_IMM(ctx->opcode));
break;
case OPC_RISC_ATOMIC:
if (!has_ext(ctx, RVA)) {
goto do_illegal;
}
gen_atomic(ctx, MASK_OP_ATOMIC(ctx->opcode), rd, rs1, rs2);
break;
case OPC_RISC_FMADD:
@ -1788,38 +1989,42 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
}
break;
case OPC_RISC_SYSTEM:
gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
gen_system(ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
(ctx->opcode & 0xFFF00000) >> 20);
break;
do_illegal:
default:
gen_exception_illegal(ctx);
break;
}
}
static void decode_opc(CPURISCVState *env, DisasContext *ctx)
static void decode_opc(DisasContext *ctx)
{
/* check for compressed insn */
if (extract32(ctx->opcode, 0, 2) != 3) {
if (!riscv_has_ext(env, RVC)) {
if (!has_ext(ctx, RVC)) {
gen_exception_illegal(ctx);
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 2;
decode_RV32_64C(env, ctx);
decode_RV32_64C(ctx);
}
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 4;
decode_RV32_64G(env, ctx);
decode_RV32_64G(ctx);
}
}
static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPURISCVState *env = cs->env_ptr;
ctx->pc_succ_insn = ctx->base.pc_first;
ctx->flags = ctx->base.tb->flags;
ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS;
ctx->priv_ver = env->priv_ver;
ctx->misa = env->misa;
ctx->frm = -1; /* unknown rounding mode */
}
@ -1850,14 +2055,13 @@ static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
return true;
}
static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPURISCVState *env = cpu->env_ptr;
ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
decode_opc(env, ctx);
decode_opc(ctx);
ctx->base.pc_next = ctx->pc_succ_insn;
if (ctx->base.is_jmp == DISAS_NEXT) {