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tcg/riscv: Use tcg_use_softmmu 

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
master
Richard Henderson 2023-10-01 12:35:44 -07:00
parent cf0ed30eb1
commit 4944d35910
1 changed files with 94 additions and 91 deletions
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29
tcg/riscv/tcg-target.c.inc
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@ -1245,7 +1245,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false);
a_mask = (1u << aa.align) - 1; a_mask = (1u << aa.align) - 1;
#ifdef CONFIG_SOFTMMU if (tcg_use_softmmu) {
unsigned s_bits = opc & MO_SIZE; unsigned s_bits = opc & MO_SIZE;
unsigned s_mask = (1u << s_bits) - 1; unsigned s_mask = (1u << s_bits) - 1;
int mem_index = get_mmuidx(oi); int mem_index = get_mmuidx(oi);
@ -1269,9 +1269,10 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1);
/* /*
* For aligned accesses, we check the first byte and include the alignment * For aligned accesses, we check the first byte and include the
* bits within the address. For unaligned access, we check that we don't * alignment bits within the address. For unaligned access, we
* cross pages using the address of the last byte of the access. * check that we don't cross pages using the address of the last
* byte of the access.
*/ */
addr_adj = addr_reg; addr_adj = addr_reg;
if (a_mask < s_mask) { if (a_mask < s_mask) {
@ -1303,13 +1304,15 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
if (addr_type != TCG_TYPE_I32) { if (addr_type != TCG_TYPE_I32) {
tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2); tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2);
} else if (have_zba) { } else if (have_zba) {
tcg_out_opc_reg(s, OPC_ADD_UW, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2); tcg_out_opc_reg(s, OPC_ADD_UW, TCG_REG_TMP0,
addr_reg, TCG_REG_TMP2);
} else { } else {
tcg_out_ext32u(s, TCG_REG_TMP0, addr_reg); tcg_out_ext32u(s, TCG_REG_TMP0, addr_reg);
tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP0, TCG_REG_TMP2); tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0,
TCG_REG_TMP0, TCG_REG_TMP2);
} }
*pbase = TCG_REG_TMP0; *pbase = TCG_REG_TMP0;
#else } else {
TCGReg base; TCGReg base;
if (a_mask) { if (a_mask) {
@ -1329,9 +1332,11 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
if (guest_base != 0) { if (guest_base != 0) {
base = TCG_REG_TMP0; base = TCG_REG_TMP0;
if (addr_type != TCG_TYPE_I32) { if (addr_type != TCG_TYPE_I32) {
tcg_out_opc_reg(s, OPC_ADD, base, addr_reg, TCG_GUEST_BASE_REG); tcg_out_opc_reg(s, OPC_ADD, base, addr_reg,
TCG_GUEST_BASE_REG);
} else if (have_zba) { } else if (have_zba) {
tcg_out_opc_reg(s, OPC_ADD_UW, base, addr_reg, TCG_GUEST_BASE_REG); tcg_out_opc_reg(s, OPC_ADD_UW, base, addr_reg,
TCG_GUEST_BASE_REG);
} else { } else {
tcg_out_ext32u(s, base, addr_reg); tcg_out_ext32u(s, base, addr_reg);
tcg_out_opc_reg(s, OPC_ADD, base, base, TCG_GUEST_BASE_REG); tcg_out_opc_reg(s, OPC_ADD, base, base, TCG_GUEST_BASE_REG);
@ -1343,7 +1348,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
tcg_out_ext32u(s, base, addr_reg); tcg_out_ext32u(s, base, addr_reg);
} }
*pbase = base; *pbase = base;
#endif }
return ldst; return ldst;
} }
@ -2075,12 +2080,10 @@ static void tcg_target_qemu_prologue(TCGContext *s)
TCG_REG_SP, SAVE_OFS + i * REG_SIZE); TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
} }
#if !defined(CONFIG_SOFTMMU) if (!tcg_use_softmmu && guest_base) {
if (guest_base) {
tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
} }
#endif
/* Call generated code */ /* Call generated code */
tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);