From 4b5ef0b50da39a9672524a39484512fe3ab56eb5 Mon Sep 17 00:00:00 2001
From: "Edgar E. Iglesias" <edgar.iglesias@petalogix.com>
Date: Sat, 24 Jul 2010 23:25:49 +0200
Subject: [PATCH] microblaze: Speed up base + index addressing mode

Speed up reg + reg addressing mode when any of the regs is r0.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@petalogix.com>
---
 target-microblaze/translate.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 3a766d8fea..9c0492e56a 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -788,6 +788,13 @@ static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
 
     /* Treat the fast cases first.  */
     if (!dc->type_b) {
+        /* If any of the regs is r0, return a ptr to the other.  */
+        if (dc->ra == 0) {
+            return &cpu_R[dc->rb];
+        } else if (dc->rb == 0) {
+            return &cpu_R[dc->ra];
+        }
+
         *t = tcg_temp_new();
         tcg_gen_add_tl(*t, cpu_R[dc->ra], cpu_R[dc->rb]);
         return t;