mirror of https://github.com/proxmox/mirror_qemu
MIPS patches 2016-06-24
Changes: * support IEEE 754-2008 in MIPS CPUs -----BEGIN PGP SIGNATURE----- iQEcBAABAgAGBQJXbU0yAAoJEFIRjjwLKdprgNwH+wRMihvG1CIyJ0v37OuNh0ab tuNIJ87Q7cm/Gn03otO6ziOAaQaPSunfLG3Lm+o1joob7WSWWieoqrCUBof8mCxC gSJGhykICWtfLW1Q0dtYdpOq5w3XCyh7+Ap4DWbyIBoFnlQ8OXTrjJhhk1jYqL/K PZECMl2MW+ZTYCAciRYlFcT99rL1Je/WVCWtpBF3B4zGmo3seCTNTg735GaqduKX wrj5UfQisZQ8tQWW2IUoXe2iSlj8rPYjjwZf/3+K7qx/v25bgGCHubgYw6IW6uWF 6EyT9XQPvZpydHCdaxl7BqstrX7l7F7P+ok3NvQMwmsMpKFZx1Ce5FSs67oyxG4= =/6k3 -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160624' into staging MIPS patches 2016-06-24 Changes: * support IEEE 754-2008 in MIPS CPUs # gpg: Signature made Fri 24 Jun 2016 16:09:38 BST # gpg: using RSA key 0x52118E3C0B29DA6B # gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>" # Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4 4FC0 5211 8E3C 0B29 DA6B * remotes/lalrae/tags/mips-20160624: target-mips: Add FCR31's FS bit definition target-mips: Implement FCR31's R/W bitmask and related functionalities target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D> target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D> target-mips: Activate IEEE 754-2008 signaling NaN bit meaning for MSA linux-user: Update preprocessor constants for Mips-specific e_flags bits softfloat: Handle snan_bit_is_one == 0 in MIPS pickNaNMulAdd() softfloat: For Mips only, correct default NaN values softfloat: Clean code format in fpu/softfloat-specialize.h softfloat: Implement run-time-configurable meaning of signaling NaN bit Signed-off-by: Peter Maydell <peter.maydell@linaro.org>master
Peter Maydell
commit
4b86bac21c
File diff suppressed because it is too large
Load Diff
172
fpu/softfloat.c
172
fpu/softfloat.c
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@ -2105,7 +2105,7 @@ static float32 subFloat32Sigs(float32 a, float32 b, flag zSign,
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return propagateFloat32NaN(a, b, status);
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}
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float_raise(float_flag_invalid, status);
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return float32_default_nan;
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return float32_default_nan(status);
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}
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if ( aExp == 0 ) {
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aExp = 1;
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@ -2234,7 +2234,7 @@ float32 float32_mul(float32 a, float32 b, float_status *status)
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}
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if ( ( bExp | bSig ) == 0 ) {
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float_raise(float_flag_invalid, status);
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return float32_default_nan;
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return float32_default_nan(status);
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}
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return packFloat32( zSign, 0xFF, 0 );
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}
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@ -2244,7 +2244,7 @@ float32 float32_mul(float32 a, float32 b, float_status *status)
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}
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if ( ( aExp | aSig ) == 0 ) {
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float_raise(float_flag_invalid, status);
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return float32_default_nan;
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return float32_default_nan(status);
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}
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return packFloat32( zSign, 0xFF, 0 );
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}
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@ -2299,7 +2299,7 @@ float32 float32_div(float32 a, float32 b, float_status *status)
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return propagateFloat32NaN(a, b, status);
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}
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float_raise(float_flag_invalid, status);
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return float32_default_nan;
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return float32_default_nan(status);
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}
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return packFloat32( zSign, 0xFF, 0 );
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}
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@ -2313,7 +2313,7 @@ float32 float32_div(float32 a, float32 b, float_status *status)
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if ( bSig == 0 ) {
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if ( ( aExp | aSig ) == 0 ) {
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float_raise(float_flag_invalid, status);
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return float32_default_nan;
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return float32_default_nan(status);
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}
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float_raise(float_flag_divbyzero, status);
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return packFloat32( zSign, 0xFF, 0 );
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@ -2367,7 +2367,7 @@ float32 float32_rem(float32 a, float32 b, float_status *status)
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return propagateFloat32NaN(a, b, status);
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}
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float_raise(float_flag_invalid, status);
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return float32_default_nan;
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return float32_default_nan(status);
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}
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if ( bExp == 0xFF ) {
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if (bSig) {
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@ -2378,7 +2378,7 @@ float32 float32_rem(float32 a, float32 b, float_status *status)
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if ( bExp == 0 ) {
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if ( bSig == 0 ) {
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float_raise(float_flag_invalid, status);
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return float32_default_nan;
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return float32_default_nan(status);
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}
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normalizeFloat32Subnormal( bSig, &bExp, &bSig );
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}
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@ -2493,7 +2493,7 @@ float32 float32_muladd(float32 a, float32 b, float32 c, int flags,
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if (infzero) {
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float_raise(float_flag_invalid, status);
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return float32_default_nan;
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return float32_default_nan(status);
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}
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if (flags & float_muladd_negate_c) {
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@ -2514,7 +2514,7 @@ float32 float32_muladd(float32 a, float32 b, float32 c, int flags,
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if (pInf && (pSign ^ cSign)) {
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/* addition of opposite-signed infinities => InvalidOperation */
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float_raise(float_flag_invalid, status);
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return float32_default_nan;
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return float32_default_nan(status);
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}
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/* Otherwise generate an infinity of the same sign */
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return packFloat32(cSign ^ signflip, 0xff, 0);
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@ -2690,12 +2690,12 @@ float32 float32_sqrt(float32 a, float_status *status)
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}
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if ( ! aSign ) return a;
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float_raise(float_flag_invalid, status);
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return float32_default_nan;
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return float32_default_nan(status);
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}
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if ( aSign ) {
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if ( ( aExp | aSig ) == 0 ) return a;
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float_raise(float_flag_invalid, status);
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return float32_default_nan;
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return float32_default_nan(status);
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}
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if ( aExp == 0 ) {
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if ( aSig == 0 ) return float32_zero;
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@ -2828,7 +2828,7 @@ float32 float32_log2(float32 a, float_status *status)
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}
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if ( aSign ) {
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float_raise(float_flag_invalid, status);
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return float32_default_nan;
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return float32_default_nan(status);
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}
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if ( aExp == 0xFF ) {
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if (aSig) {
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@ -2974,7 +2974,8 @@ int float32_eq_quiet(float32 a, float32 b, float_status *status)
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if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
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|| ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
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) {
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if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) {
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if (float32_is_signaling_nan(a, status)
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|| float32_is_signaling_nan(b, status)) {
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float_raise(float_flag_invalid, status);
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}
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return 0;
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@ -3000,7 +3001,8 @@ int float32_le_quiet(float32 a, float32 b, float_status *status)
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if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
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|| ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
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) {
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if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) {
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if (float32_is_signaling_nan(a, status)
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|| float32_is_signaling_nan(b, status)) {
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float_raise(float_flag_invalid, status);
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}
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return 0;
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@ -3031,7 +3033,8 @@ int float32_lt_quiet(float32 a, float32 b, float_status *status)
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if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
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|| ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
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) {
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if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) {
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if (float32_is_signaling_nan(a, status)
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|| float32_is_signaling_nan(b, status)) {
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float_raise(float_flag_invalid, status);
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}
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return 0;
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@ -3060,7 +3063,8 @@ int float32_unordered_quiet(float32 a, float32 b, float_status *status)
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if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
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|| ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
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) {
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if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) {
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if (float32_is_signaling_nan(a, status)
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|| float32_is_signaling_nan(b, status)) {
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float_raise(float_flag_invalid, status);
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}
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return 1;
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@ -3896,7 +3900,7 @@ static float64 subFloat64Sigs(float64 a, float64 b, flag zSign,
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return propagateFloat64NaN(a, b, status);
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}
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float_raise(float_flag_invalid, status);
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return float64_default_nan;
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return float64_default_nan(status);
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}
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if ( aExp == 0 ) {
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aExp = 1;
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@ -4023,7 +4027,7 @@ float64 float64_mul(float64 a, float64 b, float_status *status)
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}
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if ( ( bExp | bSig ) == 0 ) {
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float_raise(float_flag_invalid, status);
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return float64_default_nan;
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return float64_default_nan(status);
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}
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return packFloat64( zSign, 0x7FF, 0 );
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}
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@ -4033,7 +4037,7 @@ float64 float64_mul(float64 a, float64 b, float_status *status)
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}
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if ( ( aExp | aSig ) == 0 ) {
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float_raise(float_flag_invalid, status);
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return float64_default_nan;
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return float64_default_nan(status);
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}
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return packFloat64( zSign, 0x7FF, 0 );
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}
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@ -4090,7 +4094,7 @@ float64 float64_div(float64 a, float64 b, float_status *status)
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return propagateFloat64NaN(a, b, status);
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}
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float_raise(float_flag_invalid, status);
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return float64_default_nan;
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return float64_default_nan(status);
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}
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return packFloat64( zSign, 0x7FF, 0 );
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}
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@ -4104,7 +4108,7 @@ float64 float64_div(float64 a, float64 b, float_status *status)
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if ( bSig == 0 ) {
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if ( ( aExp | aSig ) == 0 ) {
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float_raise(float_flag_invalid, status);
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return float64_default_nan;
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return float64_default_nan(status);
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}
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float_raise(float_flag_divbyzero, status);
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return packFloat64( zSign, 0x7FF, 0 );
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@ -4162,7 +4166,7 @@ float64 float64_rem(float64 a, float64 b, float_status *status)
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return propagateFloat64NaN(a, b, status);
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}
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float_raise(float_flag_invalid, status);
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return float64_default_nan;
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return float64_default_nan(status);
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}
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if ( bExp == 0x7FF ) {
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if (bSig) {
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@ -4173,7 +4177,7 @@ float64 float64_rem(float64 a, float64 b, float_status *status)
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if ( bExp == 0 ) {
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if ( bSig == 0 ) {
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float_raise(float_flag_invalid, status);
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return float64_default_nan;
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return float64_default_nan(status);
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}
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normalizeFloat64Subnormal( bSig, &bExp, &bSig );
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}
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@ -4275,7 +4279,7 @@ float64 float64_muladd(float64 a, float64 b, float64 c, int flags,
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if (infzero) {
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float_raise(float_flag_invalid, status);
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return float64_default_nan;
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return float64_default_nan(status);
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}
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if (flags & float_muladd_negate_c) {
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@ -4296,7 +4300,7 @@ float64 float64_muladd(float64 a, float64 b, float64 c, int flags,
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if (pInf && (pSign ^ cSign)) {
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/* addition of opposite-signed infinities => InvalidOperation */
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float_raise(float_flag_invalid, status);
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return float64_default_nan;
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return float64_default_nan(status);
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}
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/* Otherwise generate an infinity of the same sign */
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return packFloat64(cSign ^ signflip, 0x7ff, 0);
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@ -4494,12 +4498,12 @@ float64 float64_sqrt(float64 a, float_status *status)
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}
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if ( ! aSign ) return a;
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float_raise(float_flag_invalid, status);
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return float64_default_nan;
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return float64_default_nan(status);
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}
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if ( aSign ) {
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if ( ( aExp | aSig ) == 0 ) return a;
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float_raise(float_flag_invalid, status);
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return float64_default_nan;
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return float64_default_nan(status);
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}
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if ( aExp == 0 ) {
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if ( aSig == 0 ) return float64_zero;
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@ -4547,7 +4551,7 @@ float64 float64_log2(float64 a, float_status *status)
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}
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if ( aSign ) {
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float_raise(float_flag_invalid, status);
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return float64_default_nan;
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return float64_default_nan(status);
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}
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if ( aExp == 0x7FF ) {
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if (aSig) {
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@ -4694,7 +4698,8 @@ int float64_eq_quiet(float64 a, float64 b, float_status *status)
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if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
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|| ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
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) {
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if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) {
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if (float64_is_signaling_nan(a, status)
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|| float64_is_signaling_nan(b, status)) {
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float_raise(float_flag_invalid, status);
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}
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return 0;
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@ -4722,7 +4727,8 @@ int float64_le_quiet(float64 a, float64 b, float_status *status)
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if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
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|| ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
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) {
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if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) {
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if (float64_is_signaling_nan(a, status)
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|| float64_is_signaling_nan(b, status)) {
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float_raise(float_flag_invalid, status);
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}
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return 0;
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@ -4753,7 +4759,8 @@ int float64_lt_quiet(float64 a, float64 b, float_status *status)
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if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
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|| ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
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) {
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if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) {
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if (float64_is_signaling_nan(a, status)
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|| float64_is_signaling_nan(b, status)) {
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float_raise(float_flag_invalid, status);
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}
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return 0;
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@ -4782,7 +4789,8 @@ int float64_unordered_quiet(float64 a, float64 b, float_status *status)
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if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
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|| ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
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) {
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if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) {
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if (float64_is_signaling_nan(a, status)
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|| float64_is_signaling_nan(b, status)) {
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float_raise(float_flag_invalid, status);
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}
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return 1;
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@ -5207,7 +5215,6 @@ static floatx80 subFloatx80Sigs(floatx80 a, floatx80 b, flag zSign,
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int32_t aExp, bExp, zExp;
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uint64_t aSig, bSig, zSig0, zSig1;
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int32_t expDiff;
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floatx80 z;
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aSig = extractFloatx80Frac( a );
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aExp = extractFloatx80Exp( a );
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@ -5221,9 +5228,7 @@ static floatx80 subFloatx80Sigs(floatx80 a, floatx80 b, flag zSign,
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return propagateFloatx80NaN(a, b, status);
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}
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float_raise(float_flag_invalid, status);
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z.low = floatx80_default_nan_low;
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z.high = floatx80_default_nan_high;
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return z;
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return floatx80_default_nan(status);
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}
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if ( aExp == 0 ) {
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aExp = 1;
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@ -5317,7 +5322,6 @@ floatx80 floatx80_mul(floatx80 a, floatx80 b, float_status *status)
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flag aSign, bSign, zSign;
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int32_t aExp, bExp, zExp;
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uint64_t aSig, bSig, zSig0, zSig1;
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floatx80 z;
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aSig = extractFloatx80Frac( a );
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aExp = extractFloatx80Exp( a );
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@ -5341,9 +5345,7 @@ floatx80 floatx80_mul(floatx80 a, floatx80 b, float_status *status)
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if ( ( aExp | aSig ) == 0 ) {
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invalid:
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float_raise(float_flag_invalid, status);
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z.low = floatx80_default_nan_low;
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z.high = floatx80_default_nan_high;
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return z;
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return floatx80_default_nan(status);
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}
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return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
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}
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@ -5377,7 +5379,6 @@ floatx80 floatx80_div(floatx80 a, floatx80 b, float_status *status)
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int32_t aExp, bExp, zExp;
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uint64_t aSig, bSig, zSig0, zSig1;
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uint64_t rem0, rem1, rem2, term0, term1, term2;
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floatx80 z;
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aSig = extractFloatx80Frac( a );
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aExp = extractFloatx80Exp( a );
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@ -5409,9 +5410,7 @@ floatx80 floatx80_div(floatx80 a, floatx80 b, float_status *status)
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if ( ( aExp | aSig ) == 0 ) {
|
||||
invalid:
|
||||
float_raise(float_flag_invalid, status);
|
||||
z.low = floatx80_default_nan_low;
|
||||
z.high = floatx80_default_nan_high;
|
||||
return z;
|
||||
return floatx80_default_nan(status);
|
||||
}
|
||||
float_raise(float_flag_divbyzero, status);
|
||||
return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
|
||||
|
|
@ -5461,7 +5460,6 @@ floatx80 floatx80_rem(floatx80 a, floatx80 b, float_status *status)
|
|||
int32_t aExp, bExp, expDiff;
|
||||
uint64_t aSig0, aSig1, bSig;
|
||||
uint64_t q, term0, term1, alternateASig0, alternateASig1;
|
||||
floatx80 z;
|
||||
|
||||
aSig0 = extractFloatx80Frac( a );
|
||||
aExp = extractFloatx80Exp( a );
|
||||
|
|
@ -5485,9 +5483,7 @@ floatx80 floatx80_rem(floatx80 a, floatx80 b, float_status *status)
|
|||
if ( bSig == 0 ) {
|
||||
invalid:
|
||||
float_raise(float_flag_invalid, status);
|
||||
z.low = floatx80_default_nan_low;
|
||||
z.high = floatx80_default_nan_high;
|
||||
return z;
|
||||
return floatx80_default_nan(status);
|
||||
}
|
||||
normalizeFloatx80Subnormal( bSig, &bExp, &bSig );
|
||||
}
|
||||
|
|
@ -5559,7 +5555,6 @@ floatx80 floatx80_sqrt(floatx80 a, float_status *status)
|
|||
int32_t aExp, zExp;
|
||||
uint64_t aSig0, aSig1, zSig0, zSig1, doubleZSig0;
|
||||
uint64_t rem0, rem1, rem2, rem3, term0, term1, term2, term3;
|
||||
floatx80 z;
|
||||
|
||||
aSig0 = extractFloatx80Frac( a );
|
||||
aExp = extractFloatx80Exp( a );
|
||||
|
|
@ -5575,9 +5570,7 @@ floatx80 floatx80_sqrt(floatx80 a, float_status *status)
|
|||
if ( ( aExp | aSig0 ) == 0 ) return a;
|
||||
invalid:
|
||||
float_raise(float_flag_invalid, status);
|
||||
z.low = floatx80_default_nan_low;
|
||||
z.high = floatx80_default_nan_high;
|
||||
return z;
|
||||
return floatx80_default_nan(status);
|
||||
}
|
||||
if ( aExp == 0 ) {
|
||||
if ( aSig0 == 0 ) return packFloatx80( 0, 0, 0 );
|
||||
|
|
@ -5745,8 +5738,8 @@ int floatx80_eq_quiet(floatx80 a, floatx80 b, float_status *status)
|
|||
|| ( ( extractFloatx80Exp( b ) == 0x7FFF )
|
||||
&& (uint64_t) ( extractFloatx80Frac( b )<<1 ) )
|
||||
) {
|
||||
if ( floatx80_is_signaling_nan( a )
|
||||
|| floatx80_is_signaling_nan( b ) ) {
|
||||
if (floatx80_is_signaling_nan(a, status)
|
||||
|| floatx80_is_signaling_nan(b, status)) {
|
||||
float_raise(float_flag_invalid, status);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -5776,8 +5769,8 @@ int floatx80_le_quiet(floatx80 a, floatx80 b, float_status *status)
|
|||
|| ( ( extractFloatx80Exp( b ) == 0x7FFF )
|
||||
&& (uint64_t) ( extractFloatx80Frac( b )<<1 ) )
|
||||
) {
|
||||
if ( floatx80_is_signaling_nan( a )
|
||||
|| floatx80_is_signaling_nan( b ) ) {
|
||||
if (floatx80_is_signaling_nan(a, status)
|
||||
|| floatx80_is_signaling_nan(b, status)) {
|
||||
float_raise(float_flag_invalid, status);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -5812,8 +5805,8 @@ int floatx80_lt_quiet(floatx80 a, floatx80 b, float_status *status)
|
|||
|| ( ( extractFloatx80Exp( b ) == 0x7FFF )
|
||||
&& (uint64_t) ( extractFloatx80Frac( b )<<1 ) )
|
||||
) {
|
||||
if ( floatx80_is_signaling_nan( a )
|
||||
|| floatx80_is_signaling_nan( b ) ) {
|
||||
if (floatx80_is_signaling_nan(a, status)
|
||||
|| floatx80_is_signaling_nan(b, status)) {
|
||||
float_raise(float_flag_invalid, status);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -5845,8 +5838,8 @@ int floatx80_unordered_quiet(floatx80 a, floatx80 b, float_status *status)
|
|||
|| ( ( extractFloatx80Exp( b ) == 0x7FFF )
|
||||
&& (uint64_t) ( extractFloatx80Frac( b )<<1 ) )
|
||||
) {
|
||||
if ( floatx80_is_signaling_nan( a )
|
||||
|| floatx80_is_signaling_nan( b ) ) {
|
||||
if (floatx80_is_signaling_nan(a, status)
|
||||
|| floatx80_is_signaling_nan(b, status)) {
|
||||
float_raise(float_flag_invalid, status);
|
||||
}
|
||||
return 1;
|
||||
|
|
@ -6385,7 +6378,6 @@ static float128 subFloat128Sigs(float128 a, float128 b, flag zSign,
|
|||
int32_t aExp, bExp, zExp;
|
||||
uint64_t aSig0, aSig1, bSig0, bSig1, zSig0, zSig1;
|
||||
int32_t expDiff;
|
||||
float128 z;
|
||||
|
||||
aSig1 = extractFloat128Frac1( a );
|
||||
aSig0 = extractFloat128Frac0( a );
|
||||
|
|
@ -6403,9 +6395,7 @@ static float128 subFloat128Sigs(float128 a, float128 b, flag zSign,
|
|||
return propagateFloat128NaN(a, b, status);
|
||||
}
|
||||
float_raise(float_flag_invalid, status);
|
||||
z.low = float128_default_nan_low;
|
||||
z.high = float128_default_nan_high;
|
||||
return z;
|
||||
return float128_default_nan(status);
|
||||
}
|
||||
if ( aExp == 0 ) {
|
||||
aExp = 1;
|
||||
|
|
@ -6515,7 +6505,6 @@ float128 float128_mul(float128 a, float128 b, float_status *status)
|
|||
flag aSign, bSign, zSign;
|
||||
int32_t aExp, bExp, zExp;
|
||||
uint64_t aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2, zSig3;
|
||||
float128 z;
|
||||
|
||||
aSig1 = extractFloat128Frac1( a );
|
||||
aSig0 = extractFloat128Frac0( a );
|
||||
|
|
@ -6541,9 +6530,7 @@ float128 float128_mul(float128 a, float128 b, float_status *status)
|
|||
if ( ( aExp | aSig0 | aSig1 ) == 0 ) {
|
||||
invalid:
|
||||
float_raise(float_flag_invalid, status);
|
||||
z.low = float128_default_nan_low;
|
||||
z.high = float128_default_nan_high;
|
||||
return z;
|
||||
return float128_default_nan(status);
|
||||
}
|
||||
return packFloat128( zSign, 0x7FFF, 0, 0 );
|
||||
}
|
||||
|
|
@ -6582,7 +6569,6 @@ float128 float128_div(float128 a, float128 b, float_status *status)
|
|||
int32_t aExp, bExp, zExp;
|
||||
uint64_t aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2;
|
||||
uint64_t rem0, rem1, rem2, rem3, term0, term1, term2, term3;
|
||||
float128 z;
|
||||
|
||||
aSig1 = extractFloat128Frac1( a );
|
||||
aSig0 = extractFloat128Frac0( a );
|
||||
|
|
@ -6616,9 +6602,7 @@ float128 float128_div(float128 a, float128 b, float_status *status)
|
|||
if ( ( aExp | aSig0 | aSig1 ) == 0 ) {
|
||||
invalid:
|
||||
float_raise(float_flag_invalid, status);
|
||||
z.low = float128_default_nan_low;
|
||||
z.high = float128_default_nan_high;
|
||||
return z;
|
||||
return float128_default_nan(status);
|
||||
}
|
||||
float_raise(float_flag_divbyzero, status);
|
||||
return packFloat128( zSign, 0x7FFF, 0, 0 );
|
||||
|
|
@ -6673,7 +6657,6 @@ float128 float128_rem(float128 a, float128 b, float_status *status)
|
|||
uint64_t aSig0, aSig1, bSig0, bSig1, q, term0, term1, term2;
|
||||
uint64_t allZero, alternateASig0, alternateASig1, sigMean1;
|
||||
int64_t sigMean0;
|
||||
float128 z;
|
||||
|
||||
aSig1 = extractFloat128Frac1( a );
|
||||
aSig0 = extractFloat128Frac0( a );
|
||||
|
|
@ -6699,9 +6682,7 @@ float128 float128_rem(float128 a, float128 b, float_status *status)
|
|||
if ( ( bSig0 | bSig1 ) == 0 ) {
|
||||
invalid:
|
||||
float_raise(float_flag_invalid, status);
|
||||
z.low = float128_default_nan_low;
|
||||
z.high = float128_default_nan_high;
|
||||
return z;
|
||||
return float128_default_nan(status);
|
||||
}
|
||||
normalizeFloat128Subnormal( bSig0, bSig1, &bExp, &bSig0, &bSig1 );
|
||||
}
|
||||
|
|
@ -6782,7 +6763,6 @@ float128 float128_sqrt(float128 a, float_status *status)
|
|||
int32_t aExp, zExp;
|
||||
uint64_t aSig0, aSig1, zSig0, zSig1, zSig2, doubleZSig0;
|
||||
uint64_t rem0, rem1, rem2, rem3, term0, term1, term2, term3;
|
||||
float128 z;
|
||||
|
||||
aSig1 = extractFloat128Frac1( a );
|
||||
aSig0 = extractFloat128Frac0( a );
|
||||
|
|
@ -6799,9 +6779,7 @@ float128 float128_sqrt(float128 a, float_status *status)
|
|||
if ( ( aExp | aSig0 | aSig1 ) == 0 ) return a;
|
||||
invalid:
|
||||
float_raise(float_flag_invalid, status);
|
||||
z.low = float128_default_nan_low;
|
||||
z.high = float128_default_nan_high;
|
||||
return z;
|
||||
return float128_default_nan(status);
|
||||
}
|
||||
if ( aExp == 0 ) {
|
||||
if ( ( aSig0 | aSig1 ) == 0 ) return packFloat128( 0, 0, 0, 0 );
|
||||
|
|
@ -6969,8 +6947,8 @@ int float128_eq_quiet(float128 a, float128 b, float_status *status)
|
|||
|| ( ( extractFloat128Exp( b ) == 0x7FFF )
|
||||
&& ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )
|
||||
) {
|
||||
if ( float128_is_signaling_nan( a )
|
||||
|| float128_is_signaling_nan( b ) ) {
|
||||
if (float128_is_signaling_nan(a, status)
|
||||
|| float128_is_signaling_nan(b, status)) {
|
||||
float_raise(float_flag_invalid, status);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -7000,8 +6978,8 @@ int float128_le_quiet(float128 a, float128 b, float_status *status)
|
|||
|| ( ( extractFloat128Exp( b ) == 0x7FFF )
|
||||
&& ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )
|
||||
) {
|
||||
if ( float128_is_signaling_nan( a )
|
||||
|| float128_is_signaling_nan( b ) ) {
|
||||
if (float128_is_signaling_nan(a, status)
|
||||
|| float128_is_signaling_nan(b, status)) {
|
||||
float_raise(float_flag_invalid, status);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -7036,8 +7014,8 @@ int float128_lt_quiet(float128 a, float128 b, float_status *status)
|
|||
|| ( ( extractFloat128Exp( b ) == 0x7FFF )
|
||||
&& ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )
|
||||
) {
|
||||
if ( float128_is_signaling_nan( a )
|
||||
|| float128_is_signaling_nan( b ) ) {
|
||||
if (float128_is_signaling_nan(a, status)
|
||||
|| float128_is_signaling_nan(b, status)) {
|
||||
float_raise(float_flag_invalid, status);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -7070,8 +7048,8 @@ int float128_unordered_quiet(float128 a, float128 b, float_status *status)
|
|||
|| ( ( extractFloat128Exp( b ) == 0x7FFF )
|
||||
&& ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )
|
||||
) {
|
||||
if ( float128_is_signaling_nan( a )
|
||||
|| float128_is_signaling_nan( b ) ) {
|
||||
if (float128_is_signaling_nan(a, status)
|
||||
|| float128_is_signaling_nan(b, status)) {
|
||||
float_raise(float_flag_invalid, status);
|
||||
}
|
||||
return 1;
|
||||
|
|
@ -7351,8 +7329,8 @@ static inline int float ## s ## _compare_internal(float ## s a, float ## s b,\
|
|||
( ( extractFloat ## s ## Exp( b ) == nan_exp ) && \
|
||||
extractFloat ## s ## Frac( b ) )) { \
|
||||
if (!is_quiet || \
|
||||
float ## s ## _is_signaling_nan( a ) || \
|
||||
float ## s ## _is_signaling_nan( b ) ) { \
|
||||
float ## s ## _is_signaling_nan(a, status) || \
|
||||
float ## s ## _is_signaling_nan(b, status)) { \
|
||||
float_raise(float_flag_invalid, status); \
|
||||
} \
|
||||
return float_relation_unordered; \
|
||||
|
|
@ -7401,8 +7379,8 @@ static inline int floatx80_compare_internal(floatx80 a, floatx80 b,
|
|||
( ( extractFloatx80Exp( b ) == 0x7fff ) &&
|
||||
( extractFloatx80Frac( b )<<1 ) )) {
|
||||
if (!is_quiet ||
|
||||
floatx80_is_signaling_nan( a ) ||
|
||||
floatx80_is_signaling_nan( b ) ) {
|
||||
floatx80_is_signaling_nan(a, status) ||
|
||||
floatx80_is_signaling_nan(b, status)) {
|
||||
float_raise(float_flag_invalid, status);
|
||||
}
|
||||
return float_relation_unordered;
|
||||
|
|
@ -7447,8 +7425,8 @@ static inline int float128_compare_internal(float128 a, float128 b,
|
|||
( ( extractFloat128Exp( b ) == 0x7fff ) &&
|
||||
( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )) {
|
||||
if (!is_quiet ||
|
||||
float128_is_signaling_nan( a ) ||
|
||||
float128_is_signaling_nan( b ) ) {
|
||||
float128_is_signaling_nan(a, status) ||
|
||||
float128_is_signaling_nan(b, status)) {
|
||||
float_raise(float_flag_invalid, status);
|
||||
}
|
||||
return float_relation_unordered;
|
||||
|
|
@ -7508,11 +7486,11 @@ static inline float ## s float ## s ## _minmax(float ## s a, float ## s b, \
|
|||
if (float ## s ## _is_any_nan(a) || \
|
||||
float ## s ## _is_any_nan(b)) { \
|
||||
if (isieee) { \
|
||||
if (float ## s ## _is_quiet_nan(a) && \
|
||||
if (float ## s ## _is_quiet_nan(a, status) && \
|
||||
!float ## s ##_is_any_nan(b)) { \
|
||||
return b; \
|
||||
} else if (float ## s ## _is_quiet_nan(b) && \
|
||||
!float ## s ## _is_any_nan(a)) { \
|
||||
} else if (float ## s ## _is_quiet_nan(b, status) && \
|
||||
!float ## s ## _is_any_nan(a)) { \
|
||||
return a; \
|
||||
} \
|
||||
} \
|
||||
|
|
|
|||
|
|
@ -53,6 +53,8 @@ typedef int64_t Elf64_Sxword;
|
|||
#define EF_MIPS_OPTIONS_FIRST 0x00000080
|
||||
#define EF_MIPS_32BITMODE 0x00000100
|
||||
#define EF_MIPS_ABI 0x0000f000
|
||||
#define EF_MIPS_FP64 0x00000200
|
||||
#define EF_MIPS_NAN2008 0x00000400
|
||||
#define EF_MIPS_ARCH 0xf0000000
|
||||
|
||||
/* These constants define the different elf file types */
|
||||
|
|
|
|||
|
|
@ -205,6 +205,7 @@ typedef struct float_status {
|
|||
/* should denormalised inputs go to zero and set the input_denormal flag? */
|
||||
flag flush_inputs_to_zero;
|
||||
flag default_nan_mode;
|
||||
flag snan_bit_is_one;
|
||||
} float_status;
|
||||
|
||||
static inline void set_float_detect_tininess(int val, float_status *status)
|
||||
|
|
@ -236,6 +237,10 @@ static inline void set_default_nan_mode(flag val, float_status *status)
|
|||
{
|
||||
status->default_nan_mode = val;
|
||||
}
|
||||
static inline void set_snan_bit_is_one(flag val, float_status *status)
|
||||
{
|
||||
status->snan_bit_is_one = val;
|
||||
}
|
||||
static inline int get_float_detect_tininess(float_status *status)
|
||||
{
|
||||
return status->float_detect_tininess;
|
||||
|
|
@ -342,9 +347,9 @@ float64 float16_to_float64(float16 a, flag ieee, float_status *status);
|
|||
/*----------------------------------------------------------------------------
|
||||
| Software half-precision operations.
|
||||
*----------------------------------------------------------------------------*/
|
||||
int float16_is_quiet_nan( float16 );
|
||||
int float16_is_signaling_nan( float16 );
|
||||
float16 float16_maybe_silence_nan( float16 );
|
||||
int float16_is_quiet_nan(float16, float_status *status);
|
||||
int float16_is_signaling_nan(float16, float_status *status);
|
||||
float16 float16_maybe_silence_nan(float16, float_status *status);
|
||||
|
||||
static inline int float16_is_any_nan(float16 a)
|
||||
{
|
||||
|
|
@ -354,7 +359,7 @@ static inline int float16_is_any_nan(float16 a)
|
|||
/*----------------------------------------------------------------------------
|
||||
| The pattern for a default generated half-precision NaN.
|
||||
*----------------------------------------------------------------------------*/
|
||||
extern const float16 float16_default_nan;
|
||||
float16 float16_default_nan(float_status *status);
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Software IEC/IEEE single-precision conversion routines.
|
||||
|
|
@ -404,9 +409,9 @@ float32 float32_minnum(float32, float32, float_status *status);
|
|||
float32 float32_maxnum(float32, float32, float_status *status);
|
||||
float32 float32_minnummag(float32, float32, float_status *status);
|
||||
float32 float32_maxnummag(float32, float32, float_status *status);
|
||||
int float32_is_quiet_nan( float32 );
|
||||
int float32_is_signaling_nan( float32 );
|
||||
float32 float32_maybe_silence_nan( float32 );
|
||||
int float32_is_quiet_nan(float32, float_status *status);
|
||||
int float32_is_signaling_nan(float32, float_status *status);
|
||||
float32 float32_maybe_silence_nan(float32, float_status *status);
|
||||
float32 float32_scalbn(float32, int, float_status *status);
|
||||
|
||||
static inline float32 float32_abs(float32 a)
|
||||
|
|
@ -466,7 +471,7 @@ static inline float32 float32_set_sign(float32 a, int sign)
|
|||
/*----------------------------------------------------------------------------
|
||||
| The pattern for a default generated single-precision NaN.
|
||||
*----------------------------------------------------------------------------*/
|
||||
extern const float32 float32_default_nan;
|
||||
float32 float32_default_nan(float_status *status);
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Software IEC/IEEE double-precision conversion routines.
|
||||
|
|
@ -516,9 +521,9 @@ float64 float64_minnum(float64, float64, float_status *status);
|
|||
float64 float64_maxnum(float64, float64, float_status *status);
|
||||
float64 float64_minnummag(float64, float64, float_status *status);
|
||||
float64 float64_maxnummag(float64, float64, float_status *status);
|
||||
int float64_is_quiet_nan( float64 a );
|
||||
int float64_is_signaling_nan( float64 );
|
||||
float64 float64_maybe_silence_nan( float64 );
|
||||
int float64_is_quiet_nan(float64 a, float_status *status);
|
||||
int float64_is_signaling_nan(float64, float_status *status);
|
||||
float64 float64_maybe_silence_nan(float64, float_status *status);
|
||||
float64 float64_scalbn(float64, int, float_status *status);
|
||||
|
||||
static inline float64 float64_abs(float64 a)
|
||||
|
|
@ -578,7 +583,7 @@ static inline float64 float64_set_sign(float64 a, int sign)
|
|||
/*----------------------------------------------------------------------------
|
||||
| The pattern for a default generated double-precision NaN.
|
||||
*----------------------------------------------------------------------------*/
|
||||
extern const float64 float64_default_nan;
|
||||
float64 float64_default_nan(float_status *status);
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Software IEC/IEEE extended double-precision conversion routines.
|
||||
|
|
@ -611,9 +616,9 @@ int floatx80_lt_quiet(floatx80, floatx80, float_status *status);
|
|||
int floatx80_unordered_quiet(floatx80, floatx80, float_status *status);
|
||||
int floatx80_compare(floatx80, floatx80, float_status *status);
|
||||
int floatx80_compare_quiet(floatx80, floatx80, float_status *status);
|
||||
int floatx80_is_quiet_nan( floatx80 );
|
||||
int floatx80_is_signaling_nan( floatx80 );
|
||||
floatx80 floatx80_maybe_silence_nan( floatx80 );
|
||||
int floatx80_is_quiet_nan(floatx80, float_status *status);
|
||||
int floatx80_is_signaling_nan(floatx80, float_status *status);
|
||||
floatx80 floatx80_maybe_silence_nan(floatx80, float_status *status);
|
||||
floatx80 floatx80_scalbn(floatx80, int, float_status *status);
|
||||
|
||||
static inline floatx80 floatx80_abs(floatx80 a)
|
||||
|
|
@ -663,7 +668,7 @@ static inline int floatx80_is_any_nan(floatx80 a)
|
|||
/*----------------------------------------------------------------------------
|
||||
| The pattern for a default generated extended double-precision NaN.
|
||||
*----------------------------------------------------------------------------*/
|
||||
extern const floatx80 floatx80_default_nan;
|
||||
floatx80 floatx80_default_nan(float_status *status);
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
| Software IEC/IEEE quadruple-precision conversion routines.
|
||||
|
|
@ -696,9 +701,9 @@ int float128_lt_quiet(float128, float128, float_status *status);
|
|||
int float128_unordered_quiet(float128, float128, float_status *status);
|
||||
int float128_compare(float128, float128, float_status *status);
|
||||
int float128_compare_quiet(float128, float128, float_status *status);
|
||||
int float128_is_quiet_nan( float128 );
|
||||
int float128_is_signaling_nan( float128 );
|
||||
float128 float128_maybe_silence_nan( float128 );
|
||||
int float128_is_quiet_nan(float128, float_status *status);
|
||||
int float128_is_signaling_nan(float128, float_status *status);
|
||||
float128 float128_maybe_silence_nan(float128, float_status *status);
|
||||
float128 float128_scalbn(float128, int, float_status *status);
|
||||
|
||||
static inline float128 float128_abs(float128 a)
|
||||
|
|
@ -744,6 +749,6 @@ static inline int float128_is_any_nan(float128 a)
|
|||
/*----------------------------------------------------------------------------
|
||||
| The pattern for a default generated quadruple-precision NaN.
|
||||
*----------------------------------------------------------------------------*/
|
||||
extern const float128 float128_default_nan;
|
||||
float128 float128_default_nan(float_status *status);
|
||||
|
||||
#endif /* !SOFTFLOAT_H */
|
||||
|
|
|
|||
|
|
@ -4687,6 +4687,20 @@ int main(int argc, char **argv, char **envp)
|
|||
if (regs->cp0_epc & 1) {
|
||||
env->hflags |= MIPS_HFLAG_M16;
|
||||
}
|
||||
if (((info->elf_flags & EF_MIPS_NAN2008) != 0) !=
|
||||
((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) {
|
||||
if ((env->active_fpu.fcr31_rw_bitmask &
|
||||
(1 << FCR31_NAN2008)) == 0) {
|
||||
fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n");
|
||||
exit(1);
|
||||
}
|
||||
if ((info->elf_flags & EF_MIPS_NAN2008) != 0) {
|
||||
env->active_fpu.fcr31 |= (1 << FCR31_NAN2008);
|
||||
} else {
|
||||
env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008);
|
||||
}
|
||||
restore_snan_bit_mode(env);
|
||||
}
|
||||
}
|
||||
#elif defined(TARGET_OPENRISC)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -344,12 +344,12 @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
|
|||
|
||||
if (float32_is_any_nan(a)) {
|
||||
float32 nan = a;
|
||||
if (float32_is_signaling_nan(a)) {
|
||||
if (float32_is_signaling_nan(a, fpst)) {
|
||||
float_raise(float_flag_invalid, fpst);
|
||||
nan = float32_maybe_silence_nan(a);
|
||||
nan = float32_maybe_silence_nan(a, fpst);
|
||||
}
|
||||
if (fpst->default_nan_mode) {
|
||||
nan = float32_default_nan;
|
||||
nan = float32_default_nan(fpst);
|
||||
}
|
||||
return nan;
|
||||
}
|
||||
|
|
@ -373,12 +373,12 @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
|
|||
|
||||
if (float64_is_any_nan(a)) {
|
||||
float64 nan = a;
|
||||
if (float64_is_signaling_nan(a)) {
|
||||
if (float64_is_signaling_nan(a, fpst)) {
|
||||
float_raise(float_flag_invalid, fpst);
|
||||
nan = float64_maybe_silence_nan(a);
|
||||
nan = float64_maybe_silence_nan(a, fpst);
|
||||
}
|
||||
if (fpst->default_nan_mode) {
|
||||
nan = float64_default_nan;
|
||||
nan = float64_default_nan(fpst);
|
||||
}
|
||||
return nan;
|
||||
}
|
||||
|
|
@ -407,7 +407,7 @@ float32 HELPER(fcvtx_f64_to_f32)(float64 a, CPUARMState *env)
|
|||
set_float_rounding_mode(float_round_to_zero, &tstat);
|
||||
set_float_exception_flags(0, &tstat);
|
||||
r = float64_to_float32(a, &tstat);
|
||||
r = float32_maybe_silence_nan(r);
|
||||
r = float32_maybe_silence_nan(r, &tstat);
|
||||
exflags = get_float_exception_flags(&tstat);
|
||||
if (exflags & float_flag_inexact) {
|
||||
r = make_float32(float32_val(r) | 1);
|
||||
|
|
|
|||
|
|
@ -8678,7 +8678,7 @@ float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
|
|||
/* ARM requires that S<->D conversion of any kind of NaN generates
|
||||
* a quiet NaN by forcing the most significant frac bit to 1.
|
||||
*/
|
||||
return float64_maybe_silence_nan(r);
|
||||
return float64_maybe_silence_nan(r, &env->vfp.fp_status);
|
||||
}
|
||||
|
||||
float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
|
||||
|
|
@ -8687,7 +8687,7 @@ float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
|
|||
/* ARM requires that S<->D conversion of any kind of NaN generates
|
||||
* a quiet NaN by forcing the most significant frac bit to 1.
|
||||
*/
|
||||
return float32_maybe_silence_nan(r);
|
||||
return float32_maybe_silence_nan(r, &env->vfp.fp_status);
|
||||
}
|
||||
|
||||
/* VFP3 fixed point conversion. */
|
||||
|
|
@ -8786,7 +8786,7 @@ static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
|
|||
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
|
||||
float32 r = float16_to_float32(make_float16(a), ieee, s);
|
||||
if (ieee) {
|
||||
return float32_maybe_silence_nan(r);
|
||||
return float32_maybe_silence_nan(r, s);
|
||||
}
|
||||
return r;
|
||||
}
|
||||
|
|
@ -8796,7 +8796,7 @@ static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
|
|||
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
|
||||
float16 r = float32_to_float16(a, ieee, s);
|
||||
if (ieee) {
|
||||
r = float16_maybe_silence_nan(r);
|
||||
r = float16_maybe_silence_nan(r, s);
|
||||
}
|
||||
return float16_val(r);
|
||||
}
|
||||
|
|
@ -8826,7 +8826,7 @@ float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
|
|||
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
|
||||
float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
|
||||
if (ieee) {
|
||||
return float64_maybe_silence_nan(r);
|
||||
return float64_maybe_silence_nan(r, &env->vfp.fp_status);
|
||||
}
|
||||
return r;
|
||||
}
|
||||
|
|
@ -8836,7 +8836,7 @@ uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
|
|||
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
|
||||
float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
|
||||
if (ieee) {
|
||||
r = float16_maybe_silence_nan(r);
|
||||
r = float16_maybe_silence_nan(r, &env->vfp.fp_status);
|
||||
}
|
||||
return float16_val(r);
|
||||
}
|
||||
|
|
@ -8986,12 +8986,12 @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
|
|||
|
||||
if (float32_is_any_nan(f32)) {
|
||||
float32 nan = f32;
|
||||
if (float32_is_signaling_nan(f32)) {
|
||||
if (float32_is_signaling_nan(f32, fpst)) {
|
||||
float_raise(float_flag_invalid, fpst);
|
||||
nan = float32_maybe_silence_nan(f32);
|
||||
nan = float32_maybe_silence_nan(f32, fpst);
|
||||
}
|
||||
if (fpst->default_nan_mode) {
|
||||
nan = float32_default_nan;
|
||||
nan = float32_default_nan(fpst);
|
||||
}
|
||||
return nan;
|
||||
} else if (float32_is_infinity(f32)) {
|
||||
|
|
@ -9040,12 +9040,12 @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
|
|||
/* Deal with any special cases */
|
||||
if (float64_is_any_nan(f64)) {
|
||||
float64 nan = f64;
|
||||
if (float64_is_signaling_nan(f64)) {
|
||||
if (float64_is_signaling_nan(f64, fpst)) {
|
||||
float_raise(float_flag_invalid, fpst);
|
||||
nan = float64_maybe_silence_nan(f64);
|
||||
nan = float64_maybe_silence_nan(f64, fpst);
|
||||
}
|
||||
if (fpst->default_nan_mode) {
|
||||
nan = float64_default_nan;
|
||||
nan = float64_default_nan(fpst);
|
||||
}
|
||||
return nan;
|
||||
} else if (float64_is_infinity(f64)) {
|
||||
|
|
@ -9147,12 +9147,12 @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
|
|||
|
||||
if (float32_is_any_nan(f32)) {
|
||||
float32 nan = f32;
|
||||
if (float32_is_signaling_nan(f32)) {
|
||||
if (float32_is_signaling_nan(f32, s)) {
|
||||
float_raise(float_flag_invalid, s);
|
||||
nan = float32_maybe_silence_nan(f32);
|
||||
nan = float32_maybe_silence_nan(f32, s);
|
||||
}
|
||||
if (s->default_nan_mode) {
|
||||
nan = float32_default_nan;
|
||||
nan = float32_default_nan(s);
|
||||
}
|
||||
return nan;
|
||||
} else if (float32_is_zero(f32)) {
|
||||
|
|
@ -9160,7 +9160,7 @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
|
|||
return float32_set_sign(float32_infinity, float32_is_neg(f32));
|
||||
} else if (float32_is_neg(f32)) {
|
||||
float_raise(float_flag_invalid, s);
|
||||
return float32_default_nan;
|
||||
return float32_default_nan(s);
|
||||
} else if (float32_is_infinity(f32)) {
|
||||
return float32_zero;
|
||||
}
|
||||
|
|
@ -9211,12 +9211,12 @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
|
|||
|
||||
if (float64_is_any_nan(f64)) {
|
||||
float64 nan = f64;
|
||||
if (float64_is_signaling_nan(f64)) {
|
||||
if (float64_is_signaling_nan(f64, s)) {
|
||||
float_raise(float_flag_invalid, s);
|
||||
nan = float64_maybe_silence_nan(f64);
|
||||
nan = float64_maybe_silence_nan(f64, s);
|
||||
}
|
||||
if (s->default_nan_mode) {
|
||||
nan = float64_default_nan;
|
||||
nan = float64_default_nan(s);
|
||||
}
|
||||
return nan;
|
||||
} else if (float64_is_zero(f64)) {
|
||||
|
|
@ -9224,7 +9224,7 @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
|
|||
return float64_set_sign(float64_infinity, float64_is_neg(f64));
|
||||
} else if (float64_is_neg(f64)) {
|
||||
float_raise(float_flag_invalid, s);
|
||||
return float64_default_nan;
|
||||
return float64_default_nan(s);
|
||||
} else if (float64_is_infinity(f64)) {
|
||||
return float64_zero;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -558,10 +558,10 @@ float64 HELPER(sub_cmp_f64)(CPUM68KState *env, float64 a, float64 b)
|
|||
/* ??? Should flush denormals to zero. */
|
||||
float64 res;
|
||||
res = float64_sub(a, b, &env->fp_status);
|
||||
if (float64_is_quiet_nan(res)) {
|
||||
if (float64_is_quiet_nan(res, &env->fp_status)) {
|
||||
/* +/-inf compares equal against itself, but sub returns nan. */
|
||||
if (!float64_is_quiet_nan(a)
|
||||
&& !float64_is_quiet_nan(b)) {
|
||||
if (!float64_is_quiet_nan(a, &env->fp_status)
|
||||
&& !float64_is_quiet_nan(b, &env->fp_status)) {
|
||||
res = float64_zero;
|
||||
if (float64_lt_quiet(a, res, &env->fp_status))
|
||||
res = float64_chs(res);
|
||||
|
|
|
|||
|
|
@ -288,12 +288,14 @@ uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b)
|
|||
fa.l = a;
|
||||
fb.l = b;
|
||||
|
||||
if (float32_is_signaling_nan(fa.f) || float32_is_signaling_nan(fb.f)) {
|
||||
if (float32_is_signaling_nan(fa.f, &env->fp_status) ||
|
||||
float32_is_signaling_nan(fb.f, &env->fp_status)) {
|
||||
update_fpu_flags(env, float_flag_invalid);
|
||||
r = 1;
|
||||
}
|
||||
|
||||
if (float32_is_quiet_nan(fa.f) || float32_is_quiet_nan(fb.f)) {
|
||||
if (float32_is_quiet_nan(fa.f, &env->fp_status) ||
|
||||
float32_is_quiet_nan(fb.f, &env->fp_status)) {
|
||||
r = 1;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -111,7 +111,9 @@ struct CPUMIPSFPUContext {
|
|||
#define FCR0_PRID 8
|
||||
#define FCR0_REV 0
|
||||
/* fcsr */
|
||||
uint32_t fcr31_rw_bitmask;
|
||||
uint32_t fcr31;
|
||||
#define FCR31_FS 24
|
||||
#define FCR31_ABS2008 19
|
||||
#define FCR31_NAN2008 18
|
||||
#define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
|
||||
|
|
@ -825,6 +827,11 @@ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
|
|||
/* helper.c */
|
||||
int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
|
||||
int mmu_idx);
|
||||
|
||||
/* op_helper.c */
|
||||
uint32_t float_class_s(uint32_t arg, float_status *fst);
|
||||
uint64_t float_class_d(uint64_t arg, float_status *fst);
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
|
||||
hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
|
||||
|
|
@ -844,14 +851,21 @@ static inline void restore_rounding_mode(CPUMIPSState *env)
|
|||
|
||||
static inline void restore_flush_mode(CPUMIPSState *env)
|
||||
{
|
||||
set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0,
|
||||
set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0,
|
||||
&env->active_fpu.fp_status);
|
||||
}
|
||||
|
||||
static inline void restore_snan_bit_mode(CPUMIPSState *env)
|
||||
{
|
||||
set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0,
|
||||
&env->active_fpu.fp_status);
|
||||
}
|
||||
|
||||
static inline void restore_fp_status(CPUMIPSState *env)
|
||||
{
|
||||
restore_rounding_mode(env);
|
||||
restore_flush_mode(env);
|
||||
restore_snan_bit_mode(env);
|
||||
}
|
||||
|
||||
static inline void restore_msa_fp_status(CPUMIPSState *env)
|
||||
|
|
|
|||
|
|
@ -90,11 +90,9 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
|
|||
if (env->CP0_Config1 & (1 << CP0C1_FP) && n >= 38 && n < 72) {
|
||||
switch (n) {
|
||||
case 70:
|
||||
env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
|
||||
/* set rounding mode */
|
||||
restore_rounding_mode(env);
|
||||
/* set flush-to-zero mode */
|
||||
restore_flush_mode(env);
|
||||
env->active_fpu.fcr31 = (tmp & env->active_fpu.fcr31_rw_bitmask) |
|
||||
(env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask));
|
||||
restore_fp_status(env);
|
||||
break;
|
||||
case 71:
|
||||
/* FIR is read-only. Ignore writes. */
|
||||
|
|
|
|||
|
|
@ -207,8 +207,6 @@ DEF_HELPER_4(ctc1, void, env, tl, i32, i32)
|
|||
DEF_HELPER_2(float_cvtd_s, i64, env, i32)
|
||||
DEF_HELPER_2(float_cvtd_w, i64, env, i32)
|
||||
DEF_HELPER_2(float_cvtd_l, i64, env, i64)
|
||||
DEF_HELPER_2(float_cvtl_d, i64, env, i64)
|
||||
DEF_HELPER_2(float_cvtl_s, i64, env, i32)
|
||||
DEF_HELPER_2(float_cvtps_pw, i64, env, i64)
|
||||
DEF_HELPER_2(float_cvtpw_ps, i64, env, i64)
|
||||
DEF_HELPER_2(float_cvts_d, i32, env, i64)
|
||||
|
|
@ -216,14 +214,12 @@ DEF_HELPER_2(float_cvts_w, i32, env, i32)
|
|||
DEF_HELPER_2(float_cvts_l, i32, env, i64)
|
||||
DEF_HELPER_2(float_cvts_pl, i32, env, i32)
|
||||
DEF_HELPER_2(float_cvts_pu, i32, env, i32)
|
||||
DEF_HELPER_2(float_cvtw_s, i32, env, i32)
|
||||
DEF_HELPER_2(float_cvtw_d, i32, env, i64)
|
||||
|
||||
DEF_HELPER_3(float_addr_ps, i64, env, i64, i64)
|
||||
DEF_HELPER_3(float_mulr_ps, i64, env, i64, i64)
|
||||
|
||||
DEF_HELPER_FLAGS_1(float_class_s, TCG_CALL_NO_RWG_SE, i32, i32)
|
||||
DEF_HELPER_FLAGS_1(float_class_d, TCG_CALL_NO_RWG_SE, i64, i64)
|
||||
DEF_HELPER_FLAGS_2(float_class_s, TCG_CALL_NO_RWG_SE, i32, env, i32)
|
||||
DEF_HELPER_FLAGS_2(float_class_d, TCG_CALL_NO_RWG_SE, i64, env, i64)
|
||||
|
||||
#define FOP_PROTO(op) \
|
||||
DEF_HELPER_4(float_ ## op ## _s, i32, env, i32, i32, i32) \
|
||||
|
|
@ -242,14 +238,20 @@ FOP_PROTO(mina)
|
|||
#undef FOP_PROTO
|
||||
|
||||
#define FOP_PROTO(op) \
|
||||
DEF_HELPER_2(float_ ## op ## l_s, i64, env, i32) \
|
||||
DEF_HELPER_2(float_ ## op ## l_d, i64, env, i64) \
|
||||
DEF_HELPER_2(float_ ## op ## w_s, i32, env, i32) \
|
||||
DEF_HELPER_2(float_ ## op ## w_d, i32, env, i64)
|
||||
DEF_HELPER_2(float_ ## op ## _l_s, i64, env, i32) \
|
||||
DEF_HELPER_2(float_ ## op ## _l_d, i64, env, i64) \
|
||||
DEF_HELPER_2(float_ ## op ## _w_s, i32, env, i32) \
|
||||
DEF_HELPER_2(float_ ## op ## _w_d, i32, env, i64)
|
||||
FOP_PROTO(cvt)
|
||||
FOP_PROTO(round)
|
||||
FOP_PROTO(trunc)
|
||||
FOP_PROTO(ceil)
|
||||
FOP_PROTO(floor)
|
||||
FOP_PROTO(cvt_2008)
|
||||
FOP_PROTO(round_2008)
|
||||
FOP_PROTO(trunc_2008)
|
||||
FOP_PROTO(ceil_2008)
|
||||
FOP_PROTO(floor_2008)
|
||||
#undef FOP_PROTO
|
||||
|
||||
#define FOP_PROTO(op) \
|
||||
|
|
|
|||
|
|
@ -1495,11 +1495,11 @@ MSA_UNOP_DF(pcnt)
|
|||
#define FLOAT_ONE32 make_float32(0x3f8 << 20)
|
||||
#define FLOAT_ONE64 make_float64(0x3ffULL << 52)
|
||||
|
||||
#define FLOAT_SNAN16 (float16_default_nan ^ 0x0220)
|
||||
#define FLOAT_SNAN16(s) (float16_default_nan(s) ^ 0x0220)
|
||||
/* 0x7c20 */
|
||||
#define FLOAT_SNAN32 (float32_default_nan ^ 0x00400020)
|
||||
#define FLOAT_SNAN32(s) (float32_default_nan(s) ^ 0x00400020)
|
||||
/* 0x7f800020 */
|
||||
#define FLOAT_SNAN64 (float64_default_nan ^ 0x0008000000000020ULL)
|
||||
#define FLOAT_SNAN64(s) (float64_default_nan(s) ^ 0x0008000000000020ULL)
|
||||
/* 0x7ff0000000000020 */
|
||||
|
||||
static inline void clear_msacsr_cause(CPUMIPSState *env)
|
||||
|
|
@ -1612,7 +1612,7 @@ static inline float16 float16_from_float32(int32_t a, flag ieee,
|
|||
float16 f_val;
|
||||
|
||||
f_val = float32_to_float16((float32)a, ieee, status);
|
||||
f_val = float16_maybe_silence_nan(f_val);
|
||||
f_val = float16_maybe_silence_nan(f_val, status);
|
||||
|
||||
return a < 0 ? (f_val | (1 << 15)) : f_val;
|
||||
}
|
||||
|
|
@ -1622,7 +1622,7 @@ static inline float32 float32_from_float64(int64_t a, float_status *status)
|
|||
float32 f_val;
|
||||
|
||||
f_val = float64_to_float32((float64)a, status);
|
||||
f_val = float32_maybe_silence_nan(f_val);
|
||||
f_val = float32_maybe_silence_nan(f_val, status);
|
||||
|
||||
return a < 0 ? (f_val | (1 << 31)) : f_val;
|
||||
}
|
||||
|
|
@ -1633,7 +1633,7 @@ static inline float32 float32_from_float16(int16_t a, flag ieee,
|
|||
float32 f_val;
|
||||
|
||||
f_val = float16_to_float32((float16)a, ieee, status);
|
||||
f_val = float32_maybe_silence_nan(f_val);
|
||||
f_val = float32_maybe_silence_nan(f_val, status);
|
||||
|
||||
return a < 0 ? (f_val | (1 << 31)) : f_val;
|
||||
}
|
||||
|
|
@ -1643,7 +1643,7 @@ static inline float64 float64_from_float32(int32_t a, float_status *status)
|
|||
float64 f_val;
|
||||
|
||||
f_val = float32_to_float64((float64)a, status);
|
||||
f_val = float64_maybe_silence_nan(f_val);
|
||||
f_val = float64_maybe_silence_nan(f_val, status);
|
||||
|
||||
return a < 0 ? (f_val | (1ULL << 63)) : f_val;
|
||||
}
|
||||
|
|
@ -1789,7 +1789,7 @@ static inline int32_t float64_to_q32(float64 a, float_status *status)
|
|||
c = update_msacsr(env, CLEAR_IS_INEXACT, 0); \
|
||||
\
|
||||
if (get_enabled_exceptions(env, c)) { \
|
||||
DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
|
||||
DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
|
|
@ -2388,7 +2388,7 @@ void helper_msa_fsne_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
|
|||
c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
|
||||
\
|
||||
if (get_enabled_exceptions(env, c)) { \
|
||||
DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
|
||||
DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
|
|
@ -2524,7 +2524,7 @@ void helper_msa_fdiv_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
|
|||
c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
|
||||
\
|
||||
if (get_enabled_exceptions(env, c)) { \
|
||||
DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
|
||||
DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
|
|
@ -2643,7 +2643,7 @@ void helper_msa_fexp2_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
|
|||
c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
|
||||
\
|
||||
if (get_enabled_exceptions(env, c)) { \
|
||||
DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
|
||||
DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
|
|
@ -2694,7 +2694,7 @@ void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
|
|||
c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
|
||||
\
|
||||
if (get_enabled_exceptions(env, c)) { \
|
||||
DEST = ((FLOAT_SNAN ## XBITS >> 6) << 6) | c; \
|
||||
DEST = ((FLOAT_SNAN ## XBITS(status) >> 6) << 6) | c; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
|
|
@ -2731,9 +2731,9 @@ void helper_msa_ftq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
|
|||
msa_move_v(pwd, pwx);
|
||||
}
|
||||
|
||||
#define NUMBER_QNAN_PAIR(ARG1, ARG2, BITS) \
|
||||
!float ## BITS ## _is_any_nan(ARG1) \
|
||||
&& float ## BITS ## _is_quiet_nan(ARG2)
|
||||
#define NUMBER_QNAN_PAIR(ARG1, ARG2, BITS, STATUS) \
|
||||
!float ## BITS ## _is_any_nan(ARG1) \
|
||||
&& float ## BITS ## _is_quiet_nan(ARG2, STATUS)
|
||||
|
||||
#define MSA_FLOAT_MAXOP(DEST, OP, ARG1, ARG2, BITS) \
|
||||
do { \
|
||||
|
|
@ -2745,18 +2745,18 @@ void helper_msa_ftq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
|
|||
c = update_msacsr(env, 0, 0); \
|
||||
\
|
||||
if (get_enabled_exceptions(env, c)) { \
|
||||
DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
|
||||
DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define FMAXMIN_A(F, G, X, _S, _T, BITS) \
|
||||
#define FMAXMIN_A(F, G, X, _S, _T, BITS, STATUS) \
|
||||
do { \
|
||||
uint## BITS ##_t S = _S, T = _T; \
|
||||
uint## BITS ##_t as, at, xs, xt, xd; \
|
||||
if (NUMBER_QNAN_PAIR(S, T, BITS)) { \
|
||||
if (NUMBER_QNAN_PAIR(S, T, BITS, STATUS)) { \
|
||||
T = S; \
|
||||
} \
|
||||
else if (NUMBER_QNAN_PAIR(T, S, BITS)) { \
|
||||
else if (NUMBER_QNAN_PAIR(T, S, BITS, STATUS)) { \
|
||||
S = T; \
|
||||
} \
|
||||
as = float## BITS ##_abs(S); \
|
||||
|
|
@ -2770,6 +2770,7 @@ void helper_msa_ftq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
|
|||
void helper_msa_fmin_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
|
||||
uint32_t ws, uint32_t wt)
|
||||
{
|
||||
float_status *status = &env->active_tc.msa_fp_status;
|
||||
wr_t wx, *pwx = &wx;
|
||||
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
|
||||
wr_t *pws = &(env->active_fpu.fpr[ws].wr);
|
||||
|
|
@ -2781,9 +2782,9 @@ void helper_msa_fmin_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
|
|||
switch (df) {
|
||||
case DF_WORD:
|
||||
for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
|
||||
if (NUMBER_QNAN_PAIR(pws->w[i], pwt->w[i], 32)) {
|
||||
if (NUMBER_QNAN_PAIR(pws->w[i], pwt->w[i], 32, status)) {
|
||||
MSA_FLOAT_MAXOP(pwx->w[i], min, pws->w[i], pws->w[i], 32);
|
||||
} else if (NUMBER_QNAN_PAIR(pwt->w[i], pws->w[i], 32)) {
|
||||
} else if (NUMBER_QNAN_PAIR(pwt->w[i], pws->w[i], 32, status)) {
|
||||
MSA_FLOAT_MAXOP(pwx->w[i], min, pwt->w[i], pwt->w[i], 32);
|
||||
} else {
|
||||
MSA_FLOAT_MAXOP(pwx->w[i], min, pws->w[i], pwt->w[i], 32);
|
||||
|
|
@ -2792,9 +2793,9 @@ void helper_msa_fmin_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
|
|||
break;
|
||||
case DF_DOUBLE:
|
||||
for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
|
||||
if (NUMBER_QNAN_PAIR(pws->d[i], pwt->d[i], 64)) {
|
||||
if (NUMBER_QNAN_PAIR(pws->d[i], pwt->d[i], 64, status)) {
|
||||
MSA_FLOAT_MAXOP(pwx->d[i], min, pws->d[i], pws->d[i], 64);
|
||||
} else if (NUMBER_QNAN_PAIR(pwt->d[i], pws->d[i], 64)) {
|
||||
} else if (NUMBER_QNAN_PAIR(pwt->d[i], pws->d[i], 64, status)) {
|
||||
MSA_FLOAT_MAXOP(pwx->d[i], min, pwt->d[i], pwt->d[i], 64);
|
||||
} else {
|
||||
MSA_FLOAT_MAXOP(pwx->d[i], min, pws->d[i], pwt->d[i], 64);
|
||||
|
|
@ -2813,6 +2814,7 @@ void helper_msa_fmin_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
|
|||
void helper_msa_fmin_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
|
||||
uint32_t ws, uint32_t wt)
|
||||
{
|
||||
float_status *status = &env->active_tc.msa_fp_status;
|
||||
wr_t wx, *pwx = &wx;
|
||||
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
|
||||
wr_t *pws = &(env->active_fpu.fpr[ws].wr);
|
||||
|
|
@ -2824,12 +2826,12 @@ void helper_msa_fmin_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
|
|||
switch (df) {
|
||||
case DF_WORD:
|
||||
for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
|
||||
FMAXMIN_A(min, max, pwx->w[i], pws->w[i], pwt->w[i], 32);
|
||||
FMAXMIN_A(min, max, pwx->w[i], pws->w[i], pwt->w[i], 32, status);
|
||||
}
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
|
||||
FMAXMIN_A(min, max, pwx->d[i], pws->d[i], pwt->d[i], 64);
|
||||
FMAXMIN_A(min, max, pwx->d[i], pws->d[i], pwt->d[i], 64, status);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
|
|
@ -2844,6 +2846,7 @@ void helper_msa_fmin_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
|
|||
void helper_msa_fmax_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
|
||||
uint32_t ws, uint32_t wt)
|
||||
{
|
||||
float_status *status = &env->active_tc.msa_fp_status;
|
||||
wr_t wx, *pwx = &wx;
|
||||
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
|
||||
wr_t *pws = &(env->active_fpu.fpr[ws].wr);
|
||||
|
|
@ -2855,9 +2858,9 @@ void helper_msa_fmax_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
|
|||
switch (df) {
|
||||
case DF_WORD:
|
||||
for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
|
||||
if (NUMBER_QNAN_PAIR(pws->w[i], pwt->w[i], 32)) {
|
||||
if (NUMBER_QNAN_PAIR(pws->w[i], pwt->w[i], 32, status)) {
|
||||
MSA_FLOAT_MAXOP(pwx->w[i], max, pws->w[i], pws->w[i], 32);
|
||||
} else if (NUMBER_QNAN_PAIR(pwt->w[i], pws->w[i], 32)) {
|
||||
} else if (NUMBER_QNAN_PAIR(pwt->w[i], pws->w[i], 32, status)) {
|
||||
MSA_FLOAT_MAXOP(pwx->w[i], max, pwt->w[i], pwt->w[i], 32);
|
||||
} else {
|
||||
MSA_FLOAT_MAXOP(pwx->w[i], max, pws->w[i], pwt->w[i], 32);
|
||||
|
|
@ -2866,9 +2869,9 @@ void helper_msa_fmax_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
|
|||
break;
|
||||
case DF_DOUBLE:
|
||||
for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
|
||||
if (NUMBER_QNAN_PAIR(pws->d[i], pwt->d[i], 64)) {
|
||||
if (NUMBER_QNAN_PAIR(pws->d[i], pwt->d[i], 64, status)) {
|
||||
MSA_FLOAT_MAXOP(pwx->d[i], max, pws->d[i], pws->d[i], 64);
|
||||
} else if (NUMBER_QNAN_PAIR(pwt->d[i], pws->d[i], 64)) {
|
||||
} else if (NUMBER_QNAN_PAIR(pwt->d[i], pws->d[i], 64, status)) {
|
||||
MSA_FLOAT_MAXOP(pwx->d[i], max, pwt->d[i], pwt->d[i], 64);
|
||||
} else {
|
||||
MSA_FLOAT_MAXOP(pwx->d[i], max, pws->d[i], pwt->d[i], 64);
|
||||
|
|
@ -2887,6 +2890,7 @@ void helper_msa_fmax_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
|
|||
void helper_msa_fmax_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
|
||||
uint32_t ws, uint32_t wt)
|
||||
{
|
||||
float_status *status = &env->active_tc.msa_fp_status;
|
||||
wr_t wx, *pwx = &wx;
|
||||
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
|
||||
wr_t *pws = &(env->active_fpu.fpr[ws].wr);
|
||||
|
|
@ -2898,12 +2902,12 @@ void helper_msa_fmax_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
|
|||
switch (df) {
|
||||
case DF_WORD:
|
||||
for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
|
||||
FMAXMIN_A(max, min, pwx->w[i], pws->w[i], pwt->w[i], 32);
|
||||
FMAXMIN_A(max, min, pwx->w[i], pws->w[i], pwt->w[i], 32, status);
|
||||
}
|
||||
break;
|
||||
case DF_DOUBLE:
|
||||
for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
|
||||
FMAXMIN_A(max, min, pwx->d[i], pws->d[i], pwt->d[i], 64);
|
||||
FMAXMIN_A(max, min, pwx->d[i], pws->d[i], pwt->d[i], 64, status);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
|
|
@ -2918,16 +2922,18 @@ void helper_msa_fmax_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
|
|||
void helper_msa_fclass_df(CPUMIPSState *env, uint32_t df,
|
||||
uint32_t wd, uint32_t ws)
|
||||
{
|
||||
float_status* status = &env->active_tc.msa_fp_status;
|
||||
|
||||
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
|
||||
wr_t *pws = &(env->active_fpu.fpr[ws].wr);
|
||||
if (df == DF_WORD) {
|
||||
pwd->w[0] = helper_float_class_s(pws->w[0]);
|
||||
pwd->w[1] = helper_float_class_s(pws->w[1]);
|
||||
pwd->w[2] = helper_float_class_s(pws->w[2]);
|
||||
pwd->w[3] = helper_float_class_s(pws->w[3]);
|
||||
pwd->w[0] = float_class_s(pws->w[0], status);
|
||||
pwd->w[1] = float_class_s(pws->w[1], status);
|
||||
pwd->w[2] = float_class_s(pws->w[2], status);
|
||||
pwd->w[3] = float_class_s(pws->w[3], status);
|
||||
} else {
|
||||
pwd->d[0] = helper_float_class_d(pws->d[0]);
|
||||
pwd->d[1] = helper_float_class_d(pws->d[1]);
|
||||
pwd->d[0] = float_class_d(pws->d[0], status);
|
||||
pwd->d[1] = float_class_d(pws->d[1], status);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2941,7 +2947,7 @@ void helper_msa_fclass_df(CPUMIPSState *env, uint32_t df,
|
|||
c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
|
||||
\
|
||||
if (get_enabled_exceptions(env, c)) { \
|
||||
DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
|
||||
DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
|
||||
} else if (float ## BITS ## _is_any_nan(ARG)) { \
|
||||
DEST = 0; \
|
||||
} \
|
||||
|
|
@ -3045,12 +3051,12 @@ void helper_msa_fsqrt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
|
|||
set_float_exception_flags(0, status); \
|
||||
DEST = float ## BITS ## _ ## div(FLOAT_ONE ## BITS, ARG, status); \
|
||||
c = update_msacsr(env, float ## BITS ## _is_infinity(ARG) || \
|
||||
float ## BITS ## _is_quiet_nan(DEST) ? \
|
||||
float ## BITS ## _is_quiet_nan(DEST, status) ? \
|
||||
0 : RECIPROCAL_INEXACT, \
|
||||
IS_DENORMAL(DEST, BITS)); \
|
||||
\
|
||||
if (get_enabled_exceptions(env, c)) { \
|
||||
DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
|
||||
DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
|
|
@ -3166,7 +3172,7 @@ void helper_msa_frint_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
|
|||
c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
|
||||
\
|
||||
if (get_enabled_exceptions(env, c)) { \
|
||||
DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
|
||||
DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
|
|
|
|||
|
|
@ -2447,6 +2447,7 @@ void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
|
|||
|
||||
#define FLOAT_TWO32 make_float32(1 << 30)
|
||||
#define FLOAT_TWO64 make_float64(1ULL << 62)
|
||||
|
||||
#define FP_TO_INT32_OVERFLOW 0x7fffffff
|
||||
#define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
|
||||
|
||||
|
|
@ -2574,21 +2575,13 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
|
|||
((arg1 & 0x4) << 22);
|
||||
break;
|
||||
case 31:
|
||||
if (env->insn_flags & ISA_MIPS32R6) {
|
||||
uint32_t mask = 0xfefc0000;
|
||||
env->active_fpu.fcr31 = (arg1 & ~mask) |
|
||||
(env->active_fpu.fcr31 & mask);
|
||||
} else if (!(arg1 & 0x007c0000)) {
|
||||
env->active_fpu.fcr31 = arg1;
|
||||
}
|
||||
env->active_fpu.fcr31 = (arg1 & env->active_fpu.fcr31_rw_bitmask) |
|
||||
(env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask));
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
/* set rounding mode */
|
||||
restore_rounding_mode(env);
|
||||
/* set flush-to-zero mode */
|
||||
restore_flush_mode(env);
|
||||
restore_fp_status(env);
|
||||
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
||||
if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
|
||||
do_raise_exception(env, EXCP_FPE, GETPC());
|
||||
|
|
@ -2659,7 +2652,7 @@ uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
|
|||
uint64_t fdt2;
|
||||
|
||||
fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
|
||||
fdt2 = float64_maybe_silence_nan(fdt2);
|
||||
fdt2 = float64_maybe_silence_nan(fdt2, &env->active_fpu.fp_status);
|
||||
update_fcr31(env, GETPC());
|
||||
return fdt2;
|
||||
}
|
||||
|
|
@ -2682,7 +2675,7 @@ uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
|
|||
return fdt2;
|
||||
}
|
||||
|
||||
uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
uint64_t helper_float_cvt_l_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
{
|
||||
uint64_t dt2;
|
||||
|
||||
|
|
@ -2695,7 +2688,7 @@ uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
|
|||
return dt2;
|
||||
}
|
||||
|
||||
uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
|
||||
uint64_t helper_float_cvt_l_s(CPUMIPSState *env, uint32_t fst0)
|
||||
{
|
||||
uint64_t dt2;
|
||||
|
||||
|
|
@ -2749,7 +2742,7 @@ uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
|
|||
uint32_t fst2;
|
||||
|
||||
fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
|
||||
fst2 = float32_maybe_silence_nan(fst2);
|
||||
fst2 = float32_maybe_silence_nan(fst2, &env->active_fpu.fp_status);
|
||||
update_fcr31(env, GETPC());
|
||||
return fst2;
|
||||
}
|
||||
|
|
@ -2790,7 +2783,7 @@ uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
|
|||
return wt2;
|
||||
}
|
||||
|
||||
uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
|
||||
uint32_t helper_float_cvt_w_s(CPUMIPSState *env, uint32_t fst0)
|
||||
{
|
||||
uint32_t wt2;
|
||||
|
||||
|
|
@ -2803,7 +2796,7 @@ uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
|
|||
return wt2;
|
||||
}
|
||||
|
||||
uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
uint32_t helper_float_cvt_w_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
{
|
||||
uint32_t wt2;
|
||||
|
||||
|
|
@ -2816,7 +2809,7 @@ uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
|
|||
return wt2;
|
||||
}
|
||||
|
||||
uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
uint64_t helper_float_round_l_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
{
|
||||
uint64_t dt2;
|
||||
|
||||
|
|
@ -2831,7 +2824,7 @@ uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
|
|||
return dt2;
|
||||
}
|
||||
|
||||
uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
|
||||
uint64_t helper_float_round_l_s(CPUMIPSState *env, uint32_t fst0)
|
||||
{
|
||||
uint64_t dt2;
|
||||
|
||||
|
|
@ -2846,7 +2839,7 @@ uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
|
|||
return dt2;
|
||||
}
|
||||
|
||||
uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
uint32_t helper_float_round_w_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
{
|
||||
uint32_t wt2;
|
||||
|
||||
|
|
@ -2861,7 +2854,7 @@ uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
|
|||
return wt2;
|
||||
}
|
||||
|
||||
uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
|
||||
uint32_t helper_float_round_w_s(CPUMIPSState *env, uint32_t fst0)
|
||||
{
|
||||
uint32_t wt2;
|
||||
|
||||
|
|
@ -2876,7 +2869,7 @@ uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
|
|||
return wt2;
|
||||
}
|
||||
|
||||
uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
uint64_t helper_float_trunc_l_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
{
|
||||
uint64_t dt2;
|
||||
|
||||
|
|
@ -2889,7 +2882,7 @@ uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
|
|||
return dt2;
|
||||
}
|
||||
|
||||
uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
|
||||
uint64_t helper_float_trunc_l_s(CPUMIPSState *env, uint32_t fst0)
|
||||
{
|
||||
uint64_t dt2;
|
||||
|
||||
|
|
@ -2902,7 +2895,7 @@ uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
|
|||
return dt2;
|
||||
}
|
||||
|
||||
uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
uint32_t helper_float_trunc_w_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
{
|
||||
uint32_t wt2;
|
||||
|
||||
|
|
@ -2915,7 +2908,7 @@ uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
|
|||
return wt2;
|
||||
}
|
||||
|
||||
uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
|
||||
uint32_t helper_float_trunc_w_s(CPUMIPSState *env, uint32_t fst0)
|
||||
{
|
||||
uint32_t wt2;
|
||||
|
||||
|
|
@ -2928,7 +2921,7 @@ uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
|
|||
return wt2;
|
||||
}
|
||||
|
||||
uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
uint64_t helper_float_ceil_l_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
{
|
||||
uint64_t dt2;
|
||||
|
||||
|
|
@ -2943,7 +2936,7 @@ uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
|
|||
return dt2;
|
||||
}
|
||||
|
||||
uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
|
||||
uint64_t helper_float_ceil_l_s(CPUMIPSState *env, uint32_t fst0)
|
||||
{
|
||||
uint64_t dt2;
|
||||
|
||||
|
|
@ -2958,7 +2951,7 @@ uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
|
|||
return dt2;
|
||||
}
|
||||
|
||||
uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
uint32_t helper_float_ceil_w_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
{
|
||||
uint32_t wt2;
|
||||
|
||||
|
|
@ -2973,7 +2966,7 @@ uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
|
|||
return wt2;
|
||||
}
|
||||
|
||||
uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
|
||||
uint32_t helper_float_ceil_w_s(CPUMIPSState *env, uint32_t fst0)
|
||||
{
|
||||
uint32_t wt2;
|
||||
|
||||
|
|
@ -2988,7 +2981,7 @@ uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
|
|||
return wt2;
|
||||
}
|
||||
|
||||
uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
uint64_t helper_float_floor_l_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
{
|
||||
uint64_t dt2;
|
||||
|
||||
|
|
@ -3003,7 +2996,7 @@ uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
|
|||
return dt2;
|
||||
}
|
||||
|
||||
uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
|
||||
uint64_t helper_float_floor_l_s(CPUMIPSState *env, uint32_t fst0)
|
||||
{
|
||||
uint64_t dt2;
|
||||
|
||||
|
|
@ -3018,7 +3011,7 @@ uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
|
|||
return dt2;
|
||||
}
|
||||
|
||||
uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
uint32_t helper_float_floor_w_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
{
|
||||
uint32_t wt2;
|
||||
|
||||
|
|
@ -3033,7 +3026,7 @@ uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
|
|||
return wt2;
|
||||
}
|
||||
|
||||
uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
|
||||
uint32_t helper_float_floor_w_s(CPUMIPSState *env, uint32_t fst0)
|
||||
{
|
||||
uint32_t wt2;
|
||||
|
||||
|
|
@ -3048,6 +3041,334 @@ uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
|
|||
return wt2;
|
||||
}
|
||||
|
||||
uint64_t helper_float_cvt_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
{
|
||||
uint64_t dt2;
|
||||
|
||||
dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
|
||||
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
||||
& float_flag_invalid) {
|
||||
if (float64_is_any_nan(fdt0)) {
|
||||
dt2 = 0;
|
||||
}
|
||||
}
|
||||
update_fcr31(env, GETPC());
|
||||
return dt2;
|
||||
}
|
||||
|
||||
uint64_t helper_float_cvt_2008_l_s(CPUMIPSState *env, uint32_t fst0)
|
||||
{
|
||||
uint64_t dt2;
|
||||
|
||||
dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
|
||||
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
||||
& float_flag_invalid) {
|
||||
if (float32_is_any_nan(fst0)) {
|
||||
dt2 = 0;
|
||||
}
|
||||
}
|
||||
update_fcr31(env, GETPC());
|
||||
return dt2;
|
||||
}
|
||||
|
||||
uint32_t helper_float_cvt_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
{
|
||||
uint32_t wt2;
|
||||
|
||||
wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
|
||||
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
||||
& float_flag_invalid) {
|
||||
if (float64_is_any_nan(fdt0)) {
|
||||
wt2 = 0;
|
||||
}
|
||||
}
|
||||
update_fcr31(env, GETPC());
|
||||
return wt2;
|
||||
}
|
||||
|
||||
uint32_t helper_float_cvt_2008_w_s(CPUMIPSState *env, uint32_t fst0)
|
||||
{
|
||||
uint32_t wt2;
|
||||
|
||||
wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
|
||||
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
||||
& float_flag_invalid) {
|
||||
if (float32_is_any_nan(fst0)) {
|
||||
wt2 = 0;
|
||||
}
|
||||
}
|
||||
update_fcr31(env, GETPC());
|
||||
return wt2;
|
||||
}
|
||||
|
||||
uint64_t helper_float_round_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
{
|
||||
uint64_t dt2;
|
||||
|
||||
set_float_rounding_mode(float_round_nearest_even,
|
||||
&env->active_fpu.fp_status);
|
||||
dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
|
||||
restore_rounding_mode(env);
|
||||
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
||||
& float_flag_invalid) {
|
||||
if (float64_is_any_nan(fdt0)) {
|
||||
dt2 = 0;
|
||||
}
|
||||
}
|
||||
update_fcr31(env, GETPC());
|
||||
return dt2;
|
||||
}
|
||||
|
||||
uint64_t helper_float_round_2008_l_s(CPUMIPSState *env, uint32_t fst0)
|
||||
{
|
||||
uint64_t dt2;
|
||||
|
||||
set_float_rounding_mode(float_round_nearest_even,
|
||||
&env->active_fpu.fp_status);
|
||||
dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
|
||||
restore_rounding_mode(env);
|
||||
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
||||
& float_flag_invalid) {
|
||||
if (float32_is_any_nan(fst0)) {
|
||||
dt2 = 0;
|
||||
}
|
||||
}
|
||||
update_fcr31(env, GETPC());
|
||||
return dt2;
|
||||
}
|
||||
|
||||
uint32_t helper_float_round_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
{
|
||||
uint32_t wt2;
|
||||
|
||||
set_float_rounding_mode(float_round_nearest_even,
|
||||
&env->active_fpu.fp_status);
|
||||
wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
|
||||
restore_rounding_mode(env);
|
||||
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
||||
& float_flag_invalid) {
|
||||
if (float64_is_any_nan(fdt0)) {
|
||||
wt2 = 0;
|
||||
}
|
||||
}
|
||||
update_fcr31(env, GETPC());
|
||||
return wt2;
|
||||
}
|
||||
|
||||
uint32_t helper_float_round_2008_w_s(CPUMIPSState *env, uint32_t fst0)
|
||||
{
|
||||
uint32_t wt2;
|
||||
|
||||
set_float_rounding_mode(float_round_nearest_even,
|
||||
&env->active_fpu.fp_status);
|
||||
wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
|
||||
restore_rounding_mode(env);
|
||||
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
||||
& float_flag_invalid) {
|
||||
if (float32_is_any_nan(fst0)) {
|
||||
wt2 = 0;
|
||||
}
|
||||
}
|
||||
update_fcr31(env, GETPC());
|
||||
return wt2;
|
||||
}
|
||||
|
||||
uint64_t helper_float_trunc_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
{
|
||||
uint64_t dt2;
|
||||
|
||||
dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
|
||||
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
||||
& float_flag_invalid) {
|
||||
if (float64_is_any_nan(fdt0)) {
|
||||
dt2 = 0;
|
||||
}
|
||||
}
|
||||
update_fcr31(env, GETPC());
|
||||
return dt2;
|
||||
}
|
||||
|
||||
uint64_t helper_float_trunc_2008_l_s(CPUMIPSState *env, uint32_t fst0)
|
||||
{
|
||||
uint64_t dt2;
|
||||
|
||||
dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
|
||||
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
||||
& float_flag_invalid) {
|
||||
if (float32_is_any_nan(fst0)) {
|
||||
dt2 = 0;
|
||||
}
|
||||
}
|
||||
update_fcr31(env, GETPC());
|
||||
return dt2;
|
||||
}
|
||||
|
||||
uint32_t helper_float_trunc_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
{
|
||||
uint32_t wt2;
|
||||
|
||||
wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
|
||||
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
||||
& float_flag_invalid) {
|
||||
if (float64_is_any_nan(fdt0)) {
|
||||
wt2 = 0;
|
||||
}
|
||||
}
|
||||
update_fcr31(env, GETPC());
|
||||
return wt2;
|
||||
}
|
||||
|
||||
uint32_t helper_float_trunc_2008_w_s(CPUMIPSState *env, uint32_t fst0)
|
||||
{
|
||||
uint32_t wt2;
|
||||
|
||||
wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
|
||||
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
||||
& float_flag_invalid) {
|
||||
if (float32_is_any_nan(fst0)) {
|
||||
wt2 = 0;
|
||||
}
|
||||
}
|
||||
update_fcr31(env, GETPC());
|
||||
return wt2;
|
||||
}
|
||||
|
||||
uint64_t helper_float_ceil_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
{
|
||||
uint64_t dt2;
|
||||
|
||||
set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
|
||||
dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
|
||||
restore_rounding_mode(env);
|
||||
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
||||
& float_flag_invalid) {
|
||||
if (float64_is_any_nan(fdt0)) {
|
||||
dt2 = 0;
|
||||
}
|
||||
}
|
||||
update_fcr31(env, GETPC());
|
||||
return dt2;
|
||||
}
|
||||
|
||||
uint64_t helper_float_ceil_2008_l_s(CPUMIPSState *env, uint32_t fst0)
|
||||
{
|
||||
uint64_t dt2;
|
||||
|
||||
set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
|
||||
dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
|
||||
restore_rounding_mode(env);
|
||||
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
||||
& float_flag_invalid) {
|
||||
if (float32_is_any_nan(fst0)) {
|
||||
dt2 = 0;
|
||||
}
|
||||
}
|
||||
update_fcr31(env, GETPC());
|
||||
return dt2;
|
||||
}
|
||||
|
||||
uint32_t helper_float_ceil_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
{
|
||||
uint32_t wt2;
|
||||
|
||||
set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
|
||||
wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
|
||||
restore_rounding_mode(env);
|
||||
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
||||
& float_flag_invalid) {
|
||||
if (float64_is_any_nan(fdt0)) {
|
||||
wt2 = 0;
|
||||
}
|
||||
}
|
||||
update_fcr31(env, GETPC());
|
||||
return wt2;
|
||||
}
|
||||
|
||||
uint32_t helper_float_ceil_2008_w_s(CPUMIPSState *env, uint32_t fst0)
|
||||
{
|
||||
uint32_t wt2;
|
||||
|
||||
set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
|
||||
wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
|
||||
restore_rounding_mode(env);
|
||||
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
||||
& float_flag_invalid) {
|
||||
if (float32_is_any_nan(fst0)) {
|
||||
wt2 = 0;
|
||||
}
|
||||
}
|
||||
update_fcr31(env, GETPC());
|
||||
return wt2;
|
||||
}
|
||||
|
||||
uint64_t helper_float_floor_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
{
|
||||
uint64_t dt2;
|
||||
|
||||
set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
|
||||
dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
|
||||
restore_rounding_mode(env);
|
||||
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
||||
& float_flag_invalid) {
|
||||
if (float64_is_any_nan(fdt0)) {
|
||||
dt2 = 0;
|
||||
}
|
||||
}
|
||||
update_fcr31(env, GETPC());
|
||||
return dt2;
|
||||
}
|
||||
|
||||
uint64_t helper_float_floor_2008_l_s(CPUMIPSState *env, uint32_t fst0)
|
||||
{
|
||||
uint64_t dt2;
|
||||
|
||||
set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
|
||||
dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
|
||||
restore_rounding_mode(env);
|
||||
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
||||
& float_flag_invalid) {
|
||||
if (float32_is_any_nan(fst0)) {
|
||||
dt2 = 0;
|
||||
}
|
||||
}
|
||||
update_fcr31(env, GETPC());
|
||||
return dt2;
|
||||
}
|
||||
|
||||
uint32_t helper_float_floor_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
|
||||
{
|
||||
uint32_t wt2;
|
||||
|
||||
set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
|
||||
wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
|
||||
restore_rounding_mode(env);
|
||||
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
||||
& float_flag_invalid) {
|
||||
if (float64_is_any_nan(fdt0)) {
|
||||
wt2 = 0;
|
||||
}
|
||||
}
|
||||
update_fcr31(env, GETPC());
|
||||
return wt2;
|
||||
}
|
||||
|
||||
uint32_t helper_float_floor_2008_w_s(CPUMIPSState *env, uint32_t fst0)
|
||||
{
|
||||
uint32_t wt2;
|
||||
|
||||
set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
|
||||
wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
|
||||
restore_rounding_mode(env);
|
||||
if (get_float_exception_flags(&env->active_fpu.fp_status)
|
||||
& float_flag_invalid) {
|
||||
if (float32_is_any_nan(fst0)) {
|
||||
wt2 = 0;
|
||||
}
|
||||
}
|
||||
update_fcr31(env, GETPC());
|
||||
return wt2;
|
||||
}
|
||||
|
||||
/* unary operations, not modifying fp status */
|
||||
#define FLOAT_UNOP(name) \
|
||||
uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
|
||||
|
|
@ -3199,11 +3520,12 @@ FLOAT_RINT(rint_d, 64)
|
|||
#define FLOAT_CLASS_POSITIVE_ZERO 0x200
|
||||
|
||||
#define FLOAT_CLASS(name, bits) \
|
||||
uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg) \
|
||||
uint ## bits ## _t float_ ## name (uint ## bits ## _t arg, \
|
||||
float_status *status) \
|
||||
{ \
|
||||
if (float ## bits ## _is_signaling_nan(arg)) { \
|
||||
if (float ## bits ## _is_signaling_nan(arg, status)) { \
|
||||
return FLOAT_CLASS_SIGNALING_NAN; \
|
||||
} else if (float ## bits ## _is_quiet_nan(arg)) { \
|
||||
} else if (float ## bits ## _is_quiet_nan(arg, status)) { \
|
||||
return FLOAT_CLASS_QUIET_NAN; \
|
||||
} else if (float ## bits ## _is_neg(arg)) { \
|
||||
if (float ## bits ## _is_infinity(arg)) { \
|
||||
|
|
@ -3226,6 +3548,12 @@ uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg) \
|
|||
return FLOAT_CLASS_POSITIVE_NORMAL; \
|
||||
} \
|
||||
} \
|
||||
} \
|
||||
\
|
||||
uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
|
||||
uint ## bits ## _t arg) \
|
||||
{ \
|
||||
return float_ ## name(arg, &env->active_fpu.fp_status); \
|
||||
}
|
||||
|
||||
FLOAT_CLASS(class_s, 32)
|
||||
|
|
|
|||
|
|
@ -1435,6 +1435,8 @@ typedef struct DisasContext {
|
|||
bool vp;
|
||||
bool cmgcr;
|
||||
bool mrp;
|
||||
bool nan2008;
|
||||
bool abs2008;
|
||||
} DisasContext;
|
||||
|
||||
enum {
|
||||
|
|
@ -8890,7 +8892,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_helper_float_abs_s(fp0, fp0);
|
||||
if (ctx->abs2008) {
|
||||
tcg_gen_andi_i32(fp0, fp0, 0x7fffffffUL);
|
||||
} else {
|
||||
gen_helper_float_abs_s(fp0, fp0);
|
||||
}
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
}
|
||||
|
|
@ -8909,7 +8915,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_helper_float_chs_s(fp0, fp0);
|
||||
if (ctx->abs2008) {
|
||||
tcg_gen_xori_i32(fp0, fp0, 1UL << 31);
|
||||
} else {
|
||||
gen_helper_float_chs_s(fp0, fp0);
|
||||
}
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
}
|
||||
|
|
@ -8921,7 +8931,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i64 fp64 = tcg_temp_new_i64();
|
||||
|
||||
gen_load_fpr32(ctx, fp32, fs);
|
||||
gen_helper_float_roundl_s(fp64, cpu_env, fp32);
|
||||
if (ctx->nan2008) {
|
||||
gen_helper_float_round_2008_l_s(fp64, cpu_env, fp32);
|
||||
} else {
|
||||
gen_helper_float_round_l_s(fp64, cpu_env, fp32);
|
||||
}
|
||||
tcg_temp_free_i32(fp32);
|
||||
gen_store_fpr64(ctx, fp64, fd);
|
||||
tcg_temp_free_i64(fp64);
|
||||
|
|
@ -8934,7 +8948,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i64 fp64 = tcg_temp_new_i64();
|
||||
|
||||
gen_load_fpr32(ctx, fp32, fs);
|
||||
gen_helper_float_truncl_s(fp64, cpu_env, fp32);
|
||||
if (ctx->nan2008) {
|
||||
gen_helper_float_trunc_2008_l_s(fp64, cpu_env, fp32);
|
||||
} else {
|
||||
gen_helper_float_trunc_l_s(fp64, cpu_env, fp32);
|
||||
}
|
||||
tcg_temp_free_i32(fp32);
|
||||
gen_store_fpr64(ctx, fp64, fd);
|
||||
tcg_temp_free_i64(fp64);
|
||||
|
|
@ -8947,7 +8965,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i64 fp64 = tcg_temp_new_i64();
|
||||
|
||||
gen_load_fpr32(ctx, fp32, fs);
|
||||
gen_helper_float_ceill_s(fp64, cpu_env, fp32);
|
||||
if (ctx->nan2008) {
|
||||
gen_helper_float_ceil_2008_l_s(fp64, cpu_env, fp32);
|
||||
} else {
|
||||
gen_helper_float_ceil_l_s(fp64, cpu_env, fp32);
|
||||
}
|
||||
tcg_temp_free_i32(fp32);
|
||||
gen_store_fpr64(ctx, fp64, fd);
|
||||
tcg_temp_free_i64(fp64);
|
||||
|
|
@ -8960,7 +8982,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i64 fp64 = tcg_temp_new_i64();
|
||||
|
||||
gen_load_fpr32(ctx, fp32, fs);
|
||||
gen_helper_float_floorl_s(fp64, cpu_env, fp32);
|
||||
if (ctx->nan2008) {
|
||||
gen_helper_float_floor_2008_l_s(fp64, cpu_env, fp32);
|
||||
} else {
|
||||
gen_helper_float_floor_l_s(fp64, cpu_env, fp32);
|
||||
}
|
||||
tcg_temp_free_i32(fp32);
|
||||
gen_store_fpr64(ctx, fp64, fd);
|
||||
tcg_temp_free_i64(fp64);
|
||||
|
|
@ -8971,7 +8997,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_helper_float_roundw_s(fp0, cpu_env, fp0);
|
||||
if (ctx->nan2008) {
|
||||
gen_helper_float_round_2008_w_s(fp0, cpu_env, fp0);
|
||||
} else {
|
||||
gen_helper_float_round_w_s(fp0, cpu_env, fp0);
|
||||
}
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
}
|
||||
|
|
@ -8981,7 +9011,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_helper_float_truncw_s(fp0, cpu_env, fp0);
|
||||
if (ctx->nan2008) {
|
||||
gen_helper_float_trunc_2008_w_s(fp0, cpu_env, fp0);
|
||||
} else {
|
||||
gen_helper_float_trunc_w_s(fp0, cpu_env, fp0);
|
||||
}
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
}
|
||||
|
|
@ -8991,7 +9025,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_helper_float_ceilw_s(fp0, cpu_env, fp0);
|
||||
if (ctx->nan2008) {
|
||||
gen_helper_float_ceil_2008_w_s(fp0, cpu_env, fp0);
|
||||
} else {
|
||||
gen_helper_float_ceil_w_s(fp0, cpu_env, fp0);
|
||||
}
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
}
|
||||
|
|
@ -9001,7 +9039,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_helper_float_floorw_s(fp0, cpu_env, fp0);
|
||||
if (ctx->nan2008) {
|
||||
gen_helper_float_floor_2008_w_s(fp0, cpu_env, fp0);
|
||||
} else {
|
||||
gen_helper_float_floor_w_s(fp0, cpu_env, fp0);
|
||||
}
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
}
|
||||
|
|
@ -9121,7 +9163,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
{
|
||||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_helper_float_class_s(fp0, fp0);
|
||||
gen_helper_float_class_s(fp0, cpu_env, fp0);
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
}
|
||||
|
|
@ -9250,7 +9292,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i32 fp0 = tcg_temp_new_i32();
|
||||
|
||||
gen_load_fpr32(ctx, fp0, fs);
|
||||
gen_helper_float_cvtw_s(fp0, cpu_env, fp0);
|
||||
if (ctx->nan2008) {
|
||||
gen_helper_float_cvt_2008_w_s(fp0, cpu_env, fp0);
|
||||
} else {
|
||||
gen_helper_float_cvt_w_s(fp0, cpu_env, fp0);
|
||||
}
|
||||
gen_store_fpr32(ctx, fp0, fd);
|
||||
tcg_temp_free_i32(fp0);
|
||||
}
|
||||
|
|
@ -9262,7 +9308,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i64 fp64 = tcg_temp_new_i64();
|
||||
|
||||
gen_load_fpr32(ctx, fp32, fs);
|
||||
gen_helper_float_cvtl_s(fp64, cpu_env, fp32);
|
||||
if (ctx->nan2008) {
|
||||
gen_helper_float_cvt_2008_l_s(fp64, cpu_env, fp32);
|
||||
} else {
|
||||
gen_helper_float_cvt_l_s(fp64, cpu_env, fp32);
|
||||
}
|
||||
tcg_temp_free_i32(fp32);
|
||||
gen_store_fpr64(ctx, fp64, fd);
|
||||
tcg_temp_free_i64(fp64);
|
||||
|
|
@ -9380,7 +9430,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i64 fp0 = tcg_temp_new_i64();
|
||||
|
||||
gen_load_fpr64(ctx, fp0, fs);
|
||||
gen_helper_float_abs_d(fp0, fp0);
|
||||
if (ctx->abs2008) {
|
||||
tcg_gen_andi_i64(fp0, fp0, 0x7fffffffffffffffULL);
|
||||
} else {
|
||||
gen_helper_float_abs_d(fp0, fp0);
|
||||
}
|
||||
gen_store_fpr64(ctx, fp0, fd);
|
||||
tcg_temp_free_i64(fp0);
|
||||
}
|
||||
|
|
@ -9401,7 +9455,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i64 fp0 = tcg_temp_new_i64();
|
||||
|
||||
gen_load_fpr64(ctx, fp0, fs);
|
||||
gen_helper_float_chs_d(fp0, fp0);
|
||||
if (ctx->abs2008) {
|
||||
tcg_gen_xori_i64(fp0, fp0, 1ULL << 63);
|
||||
} else {
|
||||
gen_helper_float_chs_d(fp0, fp0);
|
||||
}
|
||||
gen_store_fpr64(ctx, fp0, fd);
|
||||
tcg_temp_free_i64(fp0);
|
||||
}
|
||||
|
|
@ -9412,7 +9470,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i64 fp0 = tcg_temp_new_i64();
|
||||
|
||||
gen_load_fpr64(ctx, fp0, fs);
|
||||
gen_helper_float_roundl_d(fp0, cpu_env, fp0);
|
||||
if (ctx->nan2008) {
|
||||
gen_helper_float_round_2008_l_d(fp0, cpu_env, fp0);
|
||||
} else {
|
||||
gen_helper_float_round_l_d(fp0, cpu_env, fp0);
|
||||
}
|
||||
gen_store_fpr64(ctx, fp0, fd);
|
||||
tcg_temp_free_i64(fp0);
|
||||
}
|
||||
|
|
@ -9423,7 +9485,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i64 fp0 = tcg_temp_new_i64();
|
||||
|
||||
gen_load_fpr64(ctx, fp0, fs);
|
||||
gen_helper_float_truncl_d(fp0, cpu_env, fp0);
|
||||
if (ctx->nan2008) {
|
||||
gen_helper_float_trunc_2008_l_d(fp0, cpu_env, fp0);
|
||||
} else {
|
||||
gen_helper_float_trunc_l_d(fp0, cpu_env, fp0);
|
||||
}
|
||||
gen_store_fpr64(ctx, fp0, fd);
|
||||
tcg_temp_free_i64(fp0);
|
||||
}
|
||||
|
|
@ -9434,7 +9500,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i64 fp0 = tcg_temp_new_i64();
|
||||
|
||||
gen_load_fpr64(ctx, fp0, fs);
|
||||
gen_helper_float_ceill_d(fp0, cpu_env, fp0);
|
||||
if (ctx->nan2008) {
|
||||
gen_helper_float_ceil_2008_l_d(fp0, cpu_env, fp0);
|
||||
} else {
|
||||
gen_helper_float_ceil_l_d(fp0, cpu_env, fp0);
|
||||
}
|
||||
gen_store_fpr64(ctx, fp0, fd);
|
||||
tcg_temp_free_i64(fp0);
|
||||
}
|
||||
|
|
@ -9445,7 +9515,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i64 fp0 = tcg_temp_new_i64();
|
||||
|
||||
gen_load_fpr64(ctx, fp0, fs);
|
||||
gen_helper_float_floorl_d(fp0, cpu_env, fp0);
|
||||
if (ctx->nan2008) {
|
||||
gen_helper_float_floor_2008_l_d(fp0, cpu_env, fp0);
|
||||
} else {
|
||||
gen_helper_float_floor_l_d(fp0, cpu_env, fp0);
|
||||
}
|
||||
gen_store_fpr64(ctx, fp0, fd);
|
||||
tcg_temp_free_i64(fp0);
|
||||
}
|
||||
|
|
@ -9457,7 +9531,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i64 fp64 = tcg_temp_new_i64();
|
||||
|
||||
gen_load_fpr64(ctx, fp64, fs);
|
||||
gen_helper_float_roundw_d(fp32, cpu_env, fp64);
|
||||
if (ctx->nan2008) {
|
||||
gen_helper_float_round_2008_w_d(fp32, cpu_env, fp64);
|
||||
} else {
|
||||
gen_helper_float_round_w_d(fp32, cpu_env, fp64);
|
||||
}
|
||||
tcg_temp_free_i64(fp64);
|
||||
gen_store_fpr32(ctx, fp32, fd);
|
||||
tcg_temp_free_i32(fp32);
|
||||
|
|
@ -9470,7 +9548,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i64 fp64 = tcg_temp_new_i64();
|
||||
|
||||
gen_load_fpr64(ctx, fp64, fs);
|
||||
gen_helper_float_truncw_d(fp32, cpu_env, fp64);
|
||||
if (ctx->nan2008) {
|
||||
gen_helper_float_trunc_2008_w_d(fp32, cpu_env, fp64);
|
||||
} else {
|
||||
gen_helper_float_trunc_w_d(fp32, cpu_env, fp64);
|
||||
}
|
||||
tcg_temp_free_i64(fp64);
|
||||
gen_store_fpr32(ctx, fp32, fd);
|
||||
tcg_temp_free_i32(fp32);
|
||||
|
|
@ -9483,7 +9565,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i64 fp64 = tcg_temp_new_i64();
|
||||
|
||||
gen_load_fpr64(ctx, fp64, fs);
|
||||
gen_helper_float_ceilw_d(fp32, cpu_env, fp64);
|
||||
if (ctx->nan2008) {
|
||||
gen_helper_float_ceil_2008_w_d(fp32, cpu_env, fp64);
|
||||
} else {
|
||||
gen_helper_float_ceil_w_d(fp32, cpu_env, fp64);
|
||||
}
|
||||
tcg_temp_free_i64(fp64);
|
||||
gen_store_fpr32(ctx, fp32, fd);
|
||||
tcg_temp_free_i32(fp32);
|
||||
|
|
@ -9496,7 +9582,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i64 fp64 = tcg_temp_new_i64();
|
||||
|
||||
gen_load_fpr64(ctx, fp64, fs);
|
||||
gen_helper_float_floorw_d(fp32, cpu_env, fp64);
|
||||
if (ctx->nan2008) {
|
||||
gen_helper_float_floor_2008_w_d(fp32, cpu_env, fp64);
|
||||
} else {
|
||||
gen_helper_float_floor_w_d(fp32, cpu_env, fp64);
|
||||
}
|
||||
tcg_temp_free_i64(fp64);
|
||||
gen_store_fpr32(ctx, fp32, fd);
|
||||
tcg_temp_free_i32(fp32);
|
||||
|
|
@ -9619,7 +9709,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
{
|
||||
TCGv_i64 fp0 = tcg_temp_new_i64();
|
||||
gen_load_fpr64(ctx, fp0, fs);
|
||||
gen_helper_float_class_d(fp0, fp0);
|
||||
gen_helper_float_class_d(fp0, cpu_env, fp0);
|
||||
gen_store_fpr64(ctx, fp0, fd);
|
||||
tcg_temp_free_i64(fp0);
|
||||
}
|
||||
|
|
@ -9769,7 +9859,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i64 fp64 = tcg_temp_new_i64();
|
||||
|
||||
gen_load_fpr64(ctx, fp64, fs);
|
||||
gen_helper_float_cvtw_d(fp32, cpu_env, fp64);
|
||||
if (ctx->nan2008) {
|
||||
gen_helper_float_cvt_2008_w_d(fp32, cpu_env, fp64);
|
||||
} else {
|
||||
gen_helper_float_cvt_w_d(fp32, cpu_env, fp64);
|
||||
}
|
||||
tcg_temp_free_i64(fp64);
|
||||
gen_store_fpr32(ctx, fp32, fd);
|
||||
tcg_temp_free_i32(fp32);
|
||||
|
|
@ -9781,7 +9875,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|||
TCGv_i64 fp0 = tcg_temp_new_i64();
|
||||
|
||||
gen_load_fpr64(ctx, fp0, fs);
|
||||
gen_helper_float_cvtl_d(fp0, cpu_env, fp0);
|
||||
if (ctx->nan2008) {
|
||||
gen_helper_float_cvt_2008_l_d(fp0, cpu_env, fp0);
|
||||
} else {
|
||||
gen_helper_float_cvt_l_d(fp0, cpu_env, fp0);
|
||||
}
|
||||
gen_store_fpr64(ctx, fp0, fd);
|
||||
tcg_temp_free_i64(fp0);
|
||||
}
|
||||
|
|
@ -19786,6 +19884,8 @@ void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)
|
|||
(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F));
|
||||
ctx.vp = (env->CP0_Config5 >> CP0C5_VP) & 1;
|
||||
ctx.mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
|
||||
ctx.nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;
|
||||
ctx.abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
|
||||
restore_cpu_state(env, &ctx);
|
||||
#ifdef CONFIG_USER_ONLY
|
||||
ctx.mem_idx = MIPS_HFLAG_UM;
|
||||
|
|
@ -20141,6 +20241,7 @@ void cpu_state_reset(CPUMIPSState *env)
|
|||
env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask;
|
||||
env->CP0_PageGrain = env->cpu_model->CP0_PageGrain;
|
||||
env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
|
||||
env->active_fpu.fcr31_rw_bitmask = env->cpu_model->CP1_fcr31_rw_bitmask;
|
||||
env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31;
|
||||
env->msair = env->cpu_model->MSAIR;
|
||||
env->insn_flags = env->cpu_model->insn_flags;
|
||||
|
|
@ -20251,8 +20352,7 @@ void cpu_state_reset(CPUMIPSState *env)
|
|||
}
|
||||
|
||||
compute_hflags(env);
|
||||
restore_rounding_mode(env);
|
||||
restore_flush_mode(env);
|
||||
restore_fp_status(env);
|
||||
restore_pamask(env);
|
||||
cs->exception_index = EXCP_NONE;
|
||||
|
||||
|
|
|
|||
|
|
@ -84,6 +84,7 @@ struct mips_def_t {
|
|||
int32_t CP0_TCStatus_rw_bitmask;
|
||||
int32_t CP0_SRSCtl;
|
||||
int32_t CP1_fcr0;
|
||||
int32_t CP1_fcr31_rw_bitmask;
|
||||
int32_t CP1_fcr31;
|
||||
int32_t MSAIR;
|
||||
int32_t SEGBITS;
|
||||
|
|
@ -273,6 +274,8 @@ static const mips_def_t mips_defs[] =
|
|||
.CP0_Status_rw_bitmask = 0x3678FF1F,
|
||||
.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
|
||||
(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
|
||||
.CP1_fcr31 = 0,
|
||||
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
|
||||
.SEGBITS = 32,
|
||||
.PABITS = 32,
|
||||
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
|
||||
|
|
@ -303,6 +306,8 @@ static const mips_def_t mips_defs[] =
|
|||
(0xff << CP0TCSt_TASID),
|
||||
.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
|
||||
(1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
|
||||
.CP1_fcr31 = 0,
|
||||
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
|
||||
.CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
|
||||
.CP0_SRSConf0_rw_bitmask = 0x3fffffff,
|
||||
.CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
|
||||
|
|
@ -343,6 +348,8 @@ static const mips_def_t mips_defs[] =
|
|||
.CP0_Status_rw_bitmask = 0x3778FF1F,
|
||||
.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
|
||||
(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
|
||||
.CP1_fcr31 = 0,
|
||||
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
|
||||
.SEGBITS = 32,
|
||||
.PABITS = 32,
|
||||
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
|
||||
|
|
@ -427,6 +434,7 @@ static const mips_def_t mips_defs[] =
|
|||
(1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
|
||||
(1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID),
|
||||
.CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
|
||||
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
|
||||
.SEGBITS = 32,
|
||||
.PABITS = 40,
|
||||
.insn_flags = CPU_MIPS32R5 | ASE_MSA,
|
||||
|
|
@ -465,6 +473,7 @@ static const mips_def_t mips_defs[] =
|
|||
(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
|
||||
(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
|
||||
.CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
|
||||
.CP1_fcr31_rw_bitmask = 0x0103FFFF,
|
||||
.SEGBITS = 32,
|
||||
.PABITS = 32,
|
||||
.insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS,
|
||||
|
|
@ -485,6 +494,8 @@ static const mips_def_t mips_defs[] =
|
|||
.CP0_Status_rw_bitmask = 0x3678FFFF,
|
||||
/* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
|
||||
.CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
|
||||
.CP1_fcr31 = 0,
|
||||
.CP1_fcr31_rw_bitmask = 0x0183FFFF,
|
||||
.SEGBITS = 40,
|
||||
.PABITS = 36,
|
||||
.insn_flags = CPU_MIPS3,
|
||||
|
|
@ -503,6 +514,8 @@ static const mips_def_t mips_defs[] =
|
|||
.CP0_Status_rw_bitmask = 0x3678FFFF,
|
||||
/* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
|
||||
.CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
|
||||
.CP1_fcr31 = 0,
|
||||
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
|
||||
.SEGBITS = 40,
|
||||
.PABITS = 32,
|
||||
.insn_flags = CPU_VR54XX,
|
||||
|
|
@ -548,6 +561,8 @@ static const mips_def_t mips_defs[] =
|
|||
/* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
|
||||
.CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
|
||||
(0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
|
||||
.CP1_fcr31 = 0,
|
||||
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
|
||||
.SEGBITS = 42,
|
||||
.PABITS = 36,
|
||||
.insn_flags = CPU_MIPS64,
|
||||
|
|
@ -575,6 +590,8 @@ static const mips_def_t mips_defs[] =
|
|||
.CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
|
||||
(1 << FCR0_D) | (1 << FCR0_S) |
|
||||
(0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
|
||||
.CP1_fcr31 = 0,
|
||||
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
|
||||
.SEGBITS = 40,
|
||||
.PABITS = 36,
|
||||
.insn_flags = CPU_MIPS64 | ASE_MIPS3D,
|
||||
|
|
@ -601,6 +618,8 @@ static const mips_def_t mips_defs[] =
|
|||
.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
|
||||
(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
|
||||
(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
|
||||
.CP1_fcr31 = 0,
|
||||
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
|
||||
.SEGBITS = 42,
|
||||
.PABITS = 36,
|
||||
.insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
|
||||
|
|
@ -686,6 +705,7 @@ static const mips_def_t mips_defs[] =
|
|||
(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
|
||||
(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
|
||||
.CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
|
||||
.CP1_fcr31_rw_bitmask = 0x0103FFFF,
|
||||
.SEGBITS = 48,
|
||||
.PABITS = 48,
|
||||
.insn_flags = CPU_MIPS64R6 | ASE_MSA,
|
||||
|
|
@ -704,6 +724,8 @@ static const mips_def_t mips_defs[] =
|
|||
.CCRes = 2,
|
||||
.CP0_Status_rw_bitmask = 0x35D0FFFF,
|
||||
.CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
|
||||
.CP1_fcr31 = 0,
|
||||
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
|
||||
.SEGBITS = 40,
|
||||
.PABITS = 40,
|
||||
.insn_flags = CPU_LOONGSON2E,
|
||||
|
|
@ -722,6 +744,8 @@ static const mips_def_t mips_defs[] =
|
|||
.CCRes = 2,
|
||||
.CP0_Status_rw_bitmask = 0xF5D0FF1F, /* Bits 7:5 not writable. */
|
||||
.CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
|
||||
.CP1_fcr31 = 0,
|
||||
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
|
||||
.SEGBITS = 40,
|
||||
.PABITS = 40,
|
||||
.insn_flags = CPU_LOONGSON2F,
|
||||
|
|
@ -749,6 +773,8 @@ static const mips_def_t mips_defs[] =
|
|||
.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
|
||||
(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
|
||||
(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
|
||||
.CP1_fcr31 = 0,
|
||||
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
|
||||
.SEGBITS = 42,
|
||||
.PABITS = 36,
|
||||
.insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
|
||||
|
|
@ -892,4 +918,7 @@ static void msa_reset(CPUMIPSState *env)
|
|||
|
||||
/* clear float_status nan mode */
|
||||
set_default_nan_mode(0, &env->active_tc.msa_fp_status);
|
||||
|
||||
/* set proper signanling bit meaning ("1" means "quiet") */
|
||||
set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -73,7 +73,7 @@ void helper_compute_fprf(CPUPPCState *env, uint64_t arg)
|
|||
farg.ll = arg;
|
||||
isneg = float64_is_neg(farg.d);
|
||||
if (unlikely(float64_is_any_nan(farg.d))) {
|
||||
if (float64_is_signaling_nan(farg.d)) {
|
||||
if (float64_is_signaling_nan(farg.d, &env->fp_status)) {
|
||||
/* Signaling NaN: flags are undefined */
|
||||
fprf = 0x00;
|
||||
} else {
|
||||
|
|
@ -534,8 +534,8 @@ uint64_t helper_fadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
|
|||
/* Magnitude subtraction of infinities */
|
||||
farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
|
||||
} else {
|
||||
if (unlikely(float64_is_signaling_nan(farg1.d) ||
|
||||
float64_is_signaling_nan(farg2.d))) {
|
||||
if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) ||
|
||||
float64_is_signaling_nan(farg2.d, &env->fp_status))) {
|
||||
/* sNaN addition */
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
|
||||
}
|
||||
|
|
@ -558,8 +558,8 @@ uint64_t helper_fsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
|
|||
/* Magnitude subtraction of infinities */
|
||||
farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
|
||||
} else {
|
||||
if (unlikely(float64_is_signaling_nan(farg1.d) ||
|
||||
float64_is_signaling_nan(farg2.d))) {
|
||||
if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) ||
|
||||
float64_is_signaling_nan(farg2.d, &env->fp_status))) {
|
||||
/* sNaN subtraction */
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
|
||||
}
|
||||
|
|
@ -582,8 +582,8 @@ uint64_t helper_fmul(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
|
|||
/* Multiplication of zero by infinity */
|
||||
farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
|
||||
} else {
|
||||
if (unlikely(float64_is_signaling_nan(farg1.d) ||
|
||||
float64_is_signaling_nan(farg2.d))) {
|
||||
if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) ||
|
||||
float64_is_signaling_nan(farg2.d, &env->fp_status))) {
|
||||
/* sNaN multiplication */
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
|
||||
}
|
||||
|
|
@ -609,8 +609,8 @@ uint64_t helper_fdiv(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
|
|||
/* Division of zero by zero */
|
||||
farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, 1);
|
||||
} else {
|
||||
if (unlikely(float64_is_signaling_nan(farg1.d) ||
|
||||
float64_is_signaling_nan(farg2.d))) {
|
||||
if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) ||
|
||||
float64_is_signaling_nan(farg2.d, &env->fp_status))) {
|
||||
/* sNaN division */
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
|
||||
}
|
||||
|
|
@ -632,7 +632,7 @@ uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \
|
|||
if (unlikely(env->fp_status.float_exception_flags)) { \
|
||||
if (float64_is_any_nan(arg)) { \
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1); \
|
||||
if (float64_is_signaling_nan(arg)) { \
|
||||
if (float64_is_signaling_nan(arg, &env->fp_status)) { \
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); \
|
||||
} \
|
||||
farg.ll = nanval; \
|
||||
|
|
@ -681,7 +681,7 @@ static inline uint64_t do_fri(CPUPPCState *env, uint64_t arg,
|
|||
|
||||
farg.ll = arg;
|
||||
|
||||
if (unlikely(float64_is_signaling_nan(farg.d))) {
|
||||
if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
|
||||
/* sNaN round */
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
|
||||
farg.ll = arg | 0x0008000000000000ULL;
|
||||
|
|
@ -737,9 +737,9 @@ uint64_t helper_fmadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
|
|||
/* Multiplication of zero by infinity */
|
||||
farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
|
||||
} else {
|
||||
if (unlikely(float64_is_signaling_nan(farg1.d) ||
|
||||
float64_is_signaling_nan(farg2.d) ||
|
||||
float64_is_signaling_nan(farg3.d))) {
|
||||
if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) ||
|
||||
float64_is_signaling_nan(farg2.d, &env->fp_status) ||
|
||||
float64_is_signaling_nan(farg3.d, &env->fp_status))) {
|
||||
/* sNaN operation */
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
|
||||
}
|
||||
|
|
@ -780,9 +780,9 @@ uint64_t helper_fmsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
|
|||
/* Multiplication of zero by infinity */
|
||||
farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
|
||||
} else {
|
||||
if (unlikely(float64_is_signaling_nan(farg1.d) ||
|
||||
float64_is_signaling_nan(farg2.d) ||
|
||||
float64_is_signaling_nan(farg3.d))) {
|
||||
if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) ||
|
||||
float64_is_signaling_nan(farg2.d, &env->fp_status) ||
|
||||
float64_is_signaling_nan(farg3.d, &env->fp_status))) {
|
||||
/* sNaN operation */
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
|
||||
}
|
||||
|
|
@ -821,9 +821,9 @@ uint64_t helper_fnmadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
|
|||
/* Multiplication of zero by infinity */
|
||||
farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
|
||||
} else {
|
||||
if (unlikely(float64_is_signaling_nan(farg1.d) ||
|
||||
float64_is_signaling_nan(farg2.d) ||
|
||||
float64_is_signaling_nan(farg3.d))) {
|
||||
if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) ||
|
||||
float64_is_signaling_nan(farg2.d, &env->fp_status) ||
|
||||
float64_is_signaling_nan(farg3.d, &env->fp_status))) {
|
||||
/* sNaN operation */
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
|
||||
}
|
||||
|
|
@ -866,9 +866,9 @@ uint64_t helper_fnmsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
|
|||
/* Multiplication of zero by infinity */
|
||||
farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
|
||||
} else {
|
||||
if (unlikely(float64_is_signaling_nan(farg1.d) ||
|
||||
float64_is_signaling_nan(farg2.d) ||
|
||||
float64_is_signaling_nan(farg3.d))) {
|
||||
if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) ||
|
||||
float64_is_signaling_nan(farg2.d, &env->fp_status) ||
|
||||
float64_is_signaling_nan(farg3.d, &env->fp_status))) {
|
||||
/* sNaN operation */
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
|
||||
}
|
||||
|
|
@ -903,7 +903,7 @@ uint64_t helper_frsp(CPUPPCState *env, uint64_t arg)
|
|||
|
||||
farg.ll = arg;
|
||||
|
||||
if (unlikely(float64_is_signaling_nan(farg.d))) {
|
||||
if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
|
||||
/* sNaN square root */
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
|
||||
}
|
||||
|
|
@ -921,7 +921,7 @@ uint64_t helper_fsqrt(CPUPPCState *env, uint64_t arg)
|
|||
farg.ll = arg;
|
||||
|
||||
if (unlikely(float64_is_any_nan(farg.d))) {
|
||||
if (unlikely(float64_is_signaling_nan(farg.d))) {
|
||||
if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
|
||||
/* sNaN reciprocal square root */
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
|
||||
farg.ll = float64_snan_to_qnan(farg.ll);
|
||||
|
|
@ -942,7 +942,7 @@ uint64_t helper_fre(CPUPPCState *env, uint64_t arg)
|
|||
|
||||
farg.ll = arg;
|
||||
|
||||
if (unlikely(float64_is_signaling_nan(farg.d))) {
|
||||
if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
|
||||
/* sNaN reciprocal */
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
|
||||
}
|
||||
|
|
@ -958,7 +958,7 @@ uint64_t helper_fres(CPUPPCState *env, uint64_t arg)
|
|||
|
||||
farg.ll = arg;
|
||||
|
||||
if (unlikely(float64_is_signaling_nan(farg.d))) {
|
||||
if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
|
||||
/* sNaN reciprocal */
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
|
||||
}
|
||||
|
|
@ -977,7 +977,7 @@ uint64_t helper_frsqrte(CPUPPCState *env, uint64_t arg)
|
|||
farg.ll = arg;
|
||||
|
||||
if (unlikely(float64_is_any_nan(farg.d))) {
|
||||
if (unlikely(float64_is_signaling_nan(farg.d))) {
|
||||
if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
|
||||
/* sNaN reciprocal square root */
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
|
||||
farg.ll = float64_snan_to_qnan(farg.ll);
|
||||
|
|
@ -1100,8 +1100,8 @@ void helper_fcmpu(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
|
|||
env->fpscr |= ret << FPSCR_FPRF;
|
||||
env->crf[crfD] = ret;
|
||||
if (unlikely(ret == 0x01UL
|
||||
&& (float64_is_signaling_nan(farg1.d) ||
|
||||
float64_is_signaling_nan(farg2.d)))) {
|
||||
&& (float64_is_signaling_nan(farg1.d, &env->fp_status) ||
|
||||
float64_is_signaling_nan(farg2.d, &env->fp_status)))) {
|
||||
/* sNaN comparison */
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
|
||||
}
|
||||
|
|
@ -1131,8 +1131,8 @@ void helper_fcmpo(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
|
|||
env->fpscr |= ret << FPSCR_FPRF;
|
||||
env->crf[crfD] = ret;
|
||||
if (unlikely(ret == 0x01UL)) {
|
||||
if (float64_is_signaling_nan(farg1.d) ||
|
||||
float64_is_signaling_nan(farg2.d)) {
|
||||
if (float64_is_signaling_nan(farg1.d, &env->fp_status) ||
|
||||
float64_is_signaling_nan(farg2.d, &env->fp_status)) {
|
||||
/* sNaN comparison */
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
|
||||
POWERPC_EXCP_FP_VXVC, 1);
|
||||
|
|
@ -1168,7 +1168,7 @@ static inline int32_t efsctsi(CPUPPCState *env, uint32_t val)
|
|||
|
||||
u.l = val;
|
||||
/* NaN are not treated the same way IEEE 754 does */
|
||||
if (unlikely(float32_is_quiet_nan(u.f))) {
|
||||
if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1181,7 +1181,7 @@ static inline uint32_t efsctui(CPUPPCState *env, uint32_t val)
|
|||
|
||||
u.l = val;
|
||||
/* NaN are not treated the same way IEEE 754 does */
|
||||
if (unlikely(float32_is_quiet_nan(u.f))) {
|
||||
if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1194,7 +1194,7 @@ static inline uint32_t efsctsiz(CPUPPCState *env, uint32_t val)
|
|||
|
||||
u.l = val;
|
||||
/* NaN are not treated the same way IEEE 754 does */
|
||||
if (unlikely(float32_is_quiet_nan(u.f))) {
|
||||
if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1207,7 +1207,7 @@ static inline uint32_t efsctuiz(CPUPPCState *env, uint32_t val)
|
|||
|
||||
u.l = val;
|
||||
/* NaN are not treated the same way IEEE 754 does */
|
||||
if (unlikely(float32_is_quiet_nan(u.f))) {
|
||||
if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1245,7 +1245,7 @@ static inline uint32_t efsctsf(CPUPPCState *env, uint32_t val)
|
|||
|
||||
u.l = val;
|
||||
/* NaN are not treated the same way IEEE 754 does */
|
||||
if (unlikely(float32_is_quiet_nan(u.f))) {
|
||||
if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
|
||||
return 0;
|
||||
}
|
||||
tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
|
||||
|
|
@ -1261,7 +1261,7 @@ static inline uint32_t efsctuf(CPUPPCState *env, uint32_t val)
|
|||
|
||||
u.l = val;
|
||||
/* NaN are not treated the same way IEEE 754 does */
|
||||
if (unlikely(float32_is_quiet_nan(u.f))) {
|
||||
if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
|
||||
return 0;
|
||||
}
|
||||
tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
|
||||
|
|
@ -1839,8 +1839,8 @@ void helper_##name(CPUPPCState *env, uint32_t opcode) \
|
|||
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
|
||||
if (tp##_is_infinity(xa.fld) && tp##_is_infinity(xb.fld)) { \
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, sfprf); \
|
||||
} else if (tp##_is_signaling_nan(xa.fld) || \
|
||||
tp##_is_signaling_nan(xb.fld)) { \
|
||||
} else if (tp##_is_signaling_nan(xa.fld, &tstat) || \
|
||||
tp##_is_signaling_nan(xb.fld, &tstat)) { \
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
|
||||
} \
|
||||
} \
|
||||
|
|
@ -1894,8 +1894,8 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
|
|||
if ((tp##_is_infinity(xa.fld) && tp##_is_zero(xb.fld)) || \
|
||||
(tp##_is_infinity(xb.fld) && tp##_is_zero(xa.fld))) { \
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, sfprf); \
|
||||
} else if (tp##_is_signaling_nan(xa.fld) || \
|
||||
tp##_is_signaling_nan(xb.fld)) { \
|
||||
} else if (tp##_is_signaling_nan(xa.fld, &tstat) || \
|
||||
tp##_is_signaling_nan(xb.fld, &tstat)) { \
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
|
||||
} \
|
||||
} \
|
||||
|
|
@ -1948,8 +1948,8 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
|
|||
} else if (tp##_is_zero(xa.fld) && \
|
||||
tp##_is_zero(xb.fld)) { \
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, sfprf); \
|
||||
} else if (tp##_is_signaling_nan(xa.fld) || \
|
||||
tp##_is_signaling_nan(xb.fld)) { \
|
||||
} else if (tp##_is_signaling_nan(xa.fld, &tstat) || \
|
||||
tp##_is_signaling_nan(xb.fld, &tstat)) { \
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
|
||||
} \
|
||||
} \
|
||||
|
|
@ -1990,7 +1990,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
|
|||
helper_reset_fpstatus(env); \
|
||||
\
|
||||
for (i = 0; i < nels; i++) { \
|
||||
if (unlikely(tp##_is_signaling_nan(xb.fld))) { \
|
||||
if (unlikely(tp##_is_signaling_nan(xb.fld, &env->fp_status))) { \
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
|
||||
} \
|
||||
xt.fld = tp##_div(tp##_one, xb.fld, &env->fp_status); \
|
||||
|
|
@ -2039,7 +2039,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
|
|||
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
|
||||
if (tp##_is_neg(xb.fld) && !tp##_is_zero(xb.fld)) { \
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, sfprf); \
|
||||
} else if (tp##_is_signaling_nan(xb.fld)) { \
|
||||
} else if (tp##_is_signaling_nan(xb.fld, &tstat)) { \
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
|
||||
} \
|
||||
} \
|
||||
|
|
@ -2089,7 +2089,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
|
|||
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
|
||||
if (tp##_is_neg(xb.fld) && !tp##_is_zero(xb.fld)) { \
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, sfprf); \
|
||||
} else if (tp##_is_signaling_nan(xb.fld)) { \
|
||||
} else if (tp##_is_signaling_nan(xb.fld, &tstat)) { \
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
|
||||
} \
|
||||
} \
|
||||
|
|
@ -2274,9 +2274,9 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
|
|||
env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
|
||||
\
|
||||
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
|
||||
if (tp##_is_signaling_nan(xa.fld) || \
|
||||
tp##_is_signaling_nan(b->fld) || \
|
||||
tp##_is_signaling_nan(c->fld)) { \
|
||||
if (tp##_is_signaling_nan(xa.fld, &tstat) || \
|
||||
tp##_is_signaling_nan(b->fld, &tstat) || \
|
||||
tp##_is_signaling_nan(c->fld, &tstat)) { \
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
|
||||
tstat.float_exception_flags &= ~float_flag_invalid; \
|
||||
} \
|
||||
|
|
@ -2358,8 +2358,8 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
|
|||
\
|
||||
if (unlikely(float64_is_any_nan(xa.VsrD(0)) || \
|
||||
float64_is_any_nan(xb.VsrD(0)))) { \
|
||||
if (float64_is_signaling_nan(xa.VsrD(0)) || \
|
||||
float64_is_signaling_nan(xb.VsrD(0))) { \
|
||||
if (float64_is_signaling_nan(xa.VsrD(0), &env->fp_status) || \
|
||||
float64_is_signaling_nan(xb.VsrD(0), &env->fp_status)) { \
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
|
||||
} \
|
||||
if (ordered) { \
|
||||
|
|
@ -2406,8 +2406,8 @@ void helper_##name(CPUPPCState *env, uint32_t opcode) \
|
|||
\
|
||||
for (i = 0; i < nels; i++) { \
|
||||
xt.fld = tp##_##op(xa.fld, xb.fld, &env->fp_status); \
|
||||
if (unlikely(tp##_is_signaling_nan(xa.fld) || \
|
||||
tp##_is_signaling_nan(xb.fld))) { \
|
||||
if (unlikely(tp##_is_signaling_nan(xa.fld, &env->fp_status) || \
|
||||
tp##_is_signaling_nan(xb.fld, &env->fp_status))) { \
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
|
||||
} \
|
||||
} \
|
||||
|
|
@ -2446,8 +2446,8 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
|
|||
for (i = 0; i < nels; i++) { \
|
||||
if (unlikely(tp##_is_any_nan(xa.fld) || \
|
||||
tp##_is_any_nan(xb.fld))) { \
|
||||
if (tp##_is_signaling_nan(xa.fld) || \
|
||||
tp##_is_signaling_nan(xb.fld)) { \
|
||||
if (tp##_is_signaling_nan(xa.fld, &env->fp_status) || \
|
||||
tp##_is_signaling_nan(xb.fld, &env->fp_status)) { \
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
|
||||
} \
|
||||
if (svxvc) { \
|
||||
|
|
@ -2500,7 +2500,8 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
|
|||
\
|
||||
for (i = 0; i < nels; i++) { \
|
||||
xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status); \
|
||||
if (unlikely(stp##_is_signaling_nan(xb.sfld))) { \
|
||||
if (unlikely(stp##_is_signaling_nan(xb.sfld, \
|
||||
&env->fp_status))) { \
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
|
||||
xt.tfld = ttp##_snan_to_qnan(xt.tfld); \
|
||||
} \
|
||||
|
|
@ -2555,7 +2556,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
|
|||
\
|
||||
for (i = 0; i < nels; i++) { \
|
||||
if (unlikely(stp##_is_any_nan(xb.sfld))) { \
|
||||
if (stp##_is_signaling_nan(xb.sfld)) { \
|
||||
if (stp##_is_signaling_nan(xb.sfld, &env->fp_status)) { \
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
|
||||
} \
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0); \
|
||||
|
|
@ -2664,7 +2665,8 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
|
|||
} \
|
||||
\
|
||||
for (i = 0; i < nels; i++) { \
|
||||
if (unlikely(tp##_is_signaling_nan(xb.fld))) { \
|
||||
if (unlikely(tp##_is_signaling_nan(xb.fld, \
|
||||
&env->fp_status))) { \
|
||||
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
|
||||
xt.fld = tp##_snan_to_qnan(xb.fld); \
|
||||
} else { \
|
||||
|
|
|
|||
|
|
@ -267,7 +267,7 @@ uint64_t HELPER(ldeb)(CPUS390XState *env, uint64_t f2)
|
|||
{
|
||||
float64 ret = float32_to_float64(f2, &env->fpu_status);
|
||||
handle_exceptions(env, GETPC());
|
||||
return float64_maybe_silence_nan(ret);
|
||||
return float64_maybe_silence_nan(ret, &env->fpu_status);
|
||||
}
|
||||
|
||||
/* convert 128-bit float to 64-bit float */
|
||||
|
|
@ -275,7 +275,7 @@ uint64_t HELPER(ldxb)(CPUS390XState *env, uint64_t ah, uint64_t al)
|
|||
{
|
||||
float64 ret = float128_to_float64(make_float128(ah, al), &env->fpu_status);
|
||||
handle_exceptions(env, GETPC());
|
||||
return float64_maybe_silence_nan(ret);
|
||||
return float64_maybe_silence_nan(ret, &env->fpu_status);
|
||||
}
|
||||
|
||||
/* convert 64-bit float to 128-bit float */
|
||||
|
|
@ -283,7 +283,7 @@ uint64_t HELPER(lxdb)(CPUS390XState *env, uint64_t f2)
|
|||
{
|
||||
float128 ret = float64_to_float128(f2, &env->fpu_status);
|
||||
handle_exceptions(env, GETPC());
|
||||
return RET128(float128_maybe_silence_nan(ret));
|
||||
return RET128(float128_maybe_silence_nan(ret, &env->fpu_status));
|
||||
}
|
||||
|
||||
/* convert 32-bit float to 128-bit float */
|
||||
|
|
@ -291,7 +291,7 @@ uint64_t HELPER(lxeb)(CPUS390XState *env, uint64_t f2)
|
|||
{
|
||||
float128 ret = float32_to_float128(f2, &env->fpu_status);
|
||||
handle_exceptions(env, GETPC());
|
||||
return RET128(float128_maybe_silence_nan(ret));
|
||||
return RET128(float128_maybe_silence_nan(ret, &env->fpu_status));
|
||||
}
|
||||
|
||||
/* convert 64-bit float to 32-bit float */
|
||||
|
|
@ -299,7 +299,7 @@ uint64_t HELPER(ledb)(CPUS390XState *env, uint64_t f2)
|
|||
{
|
||||
float32 ret = float64_to_float32(f2, &env->fpu_status);
|
||||
handle_exceptions(env, GETPC());
|
||||
return float32_maybe_silence_nan(ret);
|
||||
return float32_maybe_silence_nan(ret, &env->fpu_status);
|
||||
}
|
||||
|
||||
/* convert 128-bit float to 32-bit float */
|
||||
|
|
@ -307,7 +307,7 @@ uint64_t HELPER(lexb)(CPUS390XState *env, uint64_t ah, uint64_t al)
|
|||
{
|
||||
float32 ret = float128_to_float32(make_float128(ah, al), &env->fpu_status);
|
||||
handle_exceptions(env, GETPC());
|
||||
return float32_maybe_silence_nan(ret);
|
||||
return float32_maybe_silence_nan(ret, &env->fpu_status);
|
||||
}
|
||||
|
||||
/* 32-bit FP compare */
|
||||
|
|
@ -624,7 +624,7 @@ uint64_t HELPER(msdb)(CPUS390XState *env, uint64_t f1,
|
|||
}
|
||||
|
||||
/* test data class 32-bit */
|
||||
uint32_t HELPER(tceb)(uint64_t f1, uint64_t m2)
|
||||
uint32_t HELPER(tceb)(CPUS390XState *env, uint64_t f1, uint64_t m2)
|
||||
{
|
||||
float32 v1 = f1;
|
||||
int neg = float32_is_neg(v1);
|
||||
|
|
@ -633,7 +633,8 @@ uint32_t HELPER(tceb)(uint64_t f1, uint64_t m2)
|
|||
if ((float32_is_zero(v1) && (m2 & (1 << (11-neg)))) ||
|
||||
(float32_is_infinity(v1) && (m2 & (1 << (5-neg)))) ||
|
||||
(float32_is_any_nan(v1) && (m2 & (1 << (3-neg)))) ||
|
||||
(float32_is_signaling_nan(v1) && (m2 & (1 << (1-neg))))) {
|
||||
(float32_is_signaling_nan(v1, &env->fpu_status) &&
|
||||
(m2 & (1 << (1-neg))))) {
|
||||
cc = 1;
|
||||
} else if (m2 & (1 << (9-neg))) {
|
||||
/* assume normalized number */
|
||||
|
|
@ -644,7 +645,7 @@ uint32_t HELPER(tceb)(uint64_t f1, uint64_t m2)
|
|||
}
|
||||
|
||||
/* test data class 64-bit */
|
||||
uint32_t HELPER(tcdb)(uint64_t v1, uint64_t m2)
|
||||
uint32_t HELPER(tcdb)(CPUS390XState *env, uint64_t v1, uint64_t m2)
|
||||
{
|
||||
int neg = float64_is_neg(v1);
|
||||
uint32_t cc = 0;
|
||||
|
|
@ -652,7 +653,8 @@ uint32_t HELPER(tcdb)(uint64_t v1, uint64_t m2)
|
|||
if ((float64_is_zero(v1) && (m2 & (1 << (11-neg)))) ||
|
||||
(float64_is_infinity(v1) && (m2 & (1 << (5-neg)))) ||
|
||||
(float64_is_any_nan(v1) && (m2 & (1 << (3-neg)))) ||
|
||||
(float64_is_signaling_nan(v1) && (m2 & (1 << (1-neg))))) {
|
||||
(float64_is_signaling_nan(v1, &env->fpu_status) &&
|
||||
(m2 & (1 << (1-neg))))) {
|
||||
cc = 1;
|
||||
} else if (m2 & (1 << (9-neg))) {
|
||||
/* assume normalized number */
|
||||
|
|
@ -663,7 +665,8 @@ uint32_t HELPER(tcdb)(uint64_t v1, uint64_t m2)
|
|||
}
|
||||
|
||||
/* test data class 128-bit */
|
||||
uint32_t HELPER(tcxb)(uint64_t ah, uint64_t al, uint64_t m2)
|
||||
uint32_t HELPER(tcxb)(CPUS390XState *env, uint64_t ah,
|
||||
uint64_t al, uint64_t m2)
|
||||
{
|
||||
float128 v1 = make_float128(ah, al);
|
||||
int neg = float128_is_neg(v1);
|
||||
|
|
@ -672,7 +675,8 @@ uint32_t HELPER(tcxb)(uint64_t ah, uint64_t al, uint64_t m2)
|
|||
if ((float128_is_zero(v1) && (m2 & (1 << (11-neg)))) ||
|
||||
(float128_is_infinity(v1) && (m2 & (1 << (5-neg)))) ||
|
||||
(float128_is_any_nan(v1) && (m2 & (1 << (3-neg)))) ||
|
||||
(float128_is_signaling_nan(v1) && (m2 & (1 << (1-neg))))) {
|
||||
(float128_is_signaling_nan(v1, &env->fpu_status) &&
|
||||
(m2 & (1 << (1-neg))))) {
|
||||
cc = 1;
|
||||
} else if (m2 & (1 << (9-neg))) {
|
||||
/* assume normalized number */
|
||||
|
|
|
|||
|
|
@ -67,9 +67,9 @@ DEF_HELPER_FLAGS_4(maeb, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
|
|||
DEF_HELPER_FLAGS_4(madb, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
|
||||
DEF_HELPER_FLAGS_4(mseb, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
|
||||
DEF_HELPER_FLAGS_4(msdb, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
|
||||
DEF_HELPER_FLAGS_2(tceb, TCG_CALL_NO_RWG_SE, i32, i64, i64)
|
||||
DEF_HELPER_FLAGS_2(tcdb, TCG_CALL_NO_RWG_SE, i32, i64, i64)
|
||||
DEF_HELPER_FLAGS_3(tcxb, TCG_CALL_NO_RWG_SE, i32, i64, i64, i64)
|
||||
DEF_HELPER_FLAGS_3(tceb, TCG_CALL_NO_RWG_SE, i32, env, i64, i64)
|
||||
DEF_HELPER_FLAGS_3(tcdb, TCG_CALL_NO_RWG_SE, i32, env, i64, i64)
|
||||
DEF_HELPER_FLAGS_4(tcxb, TCG_CALL_NO_RWG_SE, i32, env, i64, i64, i64)
|
||||
DEF_HELPER_FLAGS_1(clz, TCG_CALL_NO_RWG_SE, i64, i64)
|
||||
DEF_HELPER_FLAGS_2(sqeb, TCG_CALL_NO_WG, i64, env, i64)
|
||||
DEF_HELPER_FLAGS_2(sqdb, TCG_CALL_NO_WG, i64, env, i64)
|
||||
|
|
|
|||
|
|
@ -3986,21 +3986,21 @@ static ExitStatus op_svc(DisasContext *s, DisasOps *o)
|
|||
|
||||
static ExitStatus op_tceb(DisasContext *s, DisasOps *o)
|
||||
{
|
||||
gen_helper_tceb(cc_op, o->in1, o->in2);
|
||||
gen_helper_tceb(cc_op, cpu_env, o->in1, o->in2);
|
||||
set_cc_static(s);
|
||||
return NO_EXIT;
|
||||
}
|
||||
|
||||
static ExitStatus op_tcdb(DisasContext *s, DisasOps *o)
|
||||
{
|
||||
gen_helper_tcdb(cc_op, o->in1, o->in2);
|
||||
gen_helper_tcdb(cc_op, cpu_env, o->in1, o->in2);
|
||||
set_cc_static(s);
|
||||
return NO_EXIT;
|
||||
}
|
||||
|
||||
static ExitStatus op_tcxb(DisasContext *s, DisasOps *o)
|
||||
{
|
||||
gen_helper_tcxb(cc_op, o->out, o->out2, o->in2);
|
||||
gen_helper_tcxb(cc_op, cpu_env, o->out, o->out2, o->in2);
|
||||
set_cc_static(s);
|
||||
return NO_EXIT;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -71,6 +71,7 @@ static void superh_cpu_reset(CPUState *s)
|
|||
set_flush_to_zero(1, &env->fp_status);
|
||||
#endif
|
||||
set_default_nan_mode(1, &env->fp_status);
|
||||
set_snan_bit_is_one(1, &env->fp_status);
|
||||
}
|
||||
|
||||
static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
|
||||
|
|
|
|||
|
|
@ -78,6 +78,7 @@ static void unicore_ii_cpu_initfn(Object *obj)
|
|||
|
||||
set_feature(env, UC32_HWCAP_CMOV);
|
||||
set_feature(env, UC32_HWCAP_UCF64);
|
||||
set_snan_bit_is_one(1, &env->ucf64.fp_status);
|
||||
}
|
||||
|
||||
static void uc32_any_cpu_initfn(Object *obj)
|
||||
|
|
@ -90,6 +91,7 @@ static void uc32_any_cpu_initfn(Object *obj)
|
|||
|
||||
set_feature(env, UC32_HWCAP_CMOV);
|
||||
set_feature(env, UC32_HWCAP_UCF64);
|
||||
set_snan_bit_is_one(1, &env->ucf64.fp_status);
|
||||
}
|
||||
|
||||
static const UniCore32CPUInfo uc32_cpus[] = {
|
||||
|
|
|
|||
Loading…
Reference in New Issue