mirror of https://github.com/proxmox/mirror_qemu
target-ppc: Add VSX ISA2.06 xdiv Instructions
This patch adds the VSX floating point divide instructions defined by V2.06 of the PowerPC ISA: xsdivdp, xvdivdp, xvdivsp. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>master
Tom Musta
Alexander Graf
parent
5e591d8812
commit
4b98eeef50
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@ -1855,3 +1855,52 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
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VSX_MUL(xsmuldp, 1, float64, f64, 1)
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VSX_MUL(xvmuldp, 2, float64, f64, 0)
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VSX_MUL(xvmulsp, 4, float32, f32, 0)
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/* VSX_DIV - VSX floating point divide
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* op - instruction mnemonic
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* nels - number of elements (1, 2 or 4)
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* tp - type (float32 or float64)
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* fld - vsr_t field (f32 or f64)
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* sfprf - set FPRF
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*/
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#define VSX_DIV(op, nels, tp, fld, sfprf) \
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void helper_##op(CPUPPCState *env, uint32_t opcode) \
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{ \
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ppc_vsr_t xt, xa, xb; \
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int i; \
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\
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getVSR(xA(opcode), &xa, env); \
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getVSR(xB(opcode), &xb, env); \
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getVSR(xT(opcode), &xt, env); \
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helper_reset_fpstatus(env); \
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\
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for (i = 0; i < nels; i++) { \
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float_status tstat = env->fp_status; \
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set_float_exception_flags(0, &tstat); \
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xt.fld[i] = tp##_div(xa.fld[i], xb.fld[i], &tstat); \
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env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
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\
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if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
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if (tp##_is_infinity(xa.fld[i]) && tp##_is_infinity(xb.fld[i])) { \
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fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI, sfprf); \
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} else if (tp##_is_zero(xa.fld[i]) && \
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tp##_is_zero(xb.fld[i])) { \
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fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, sfprf); \
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} else if (tp##_is_signaling_nan(xa.fld[i]) || \
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tp##_is_signaling_nan(xb.fld[i])) { \
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fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
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} \
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} \
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\
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if (sfprf) { \
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helper_compute_fprf(env, xt.fld[i], sfprf); \
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} \
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} \
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\
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putVSR(xT(opcode), &xt, env); \
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helper_float_check_status(env); \
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}
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VSX_DIV(xsdivdp, 1, float64, f64, 1)
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VSX_DIV(xvdivdp, 2, float64, f64, 0)
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VSX_DIV(xvdivsp, 4, float32, f32, 0)
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@ -254,14 +254,17 @@ DEF_HELPER_4(vctsxs, void, env, avr, avr, i32)
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DEF_HELPER_2(xsadddp, void, env, i32)
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DEF_HELPER_2(xssubdp, void, env, i32)
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DEF_HELPER_2(xsmuldp, void, env, i32)
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DEF_HELPER_2(xsdivdp, void, env, i32)
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DEF_HELPER_2(xvadddp, void, env, i32)
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DEF_HELPER_2(xvsubdp, void, env, i32)
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DEF_HELPER_2(xvmuldp, void, env, i32)
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DEF_HELPER_2(xvdivdp, void, env, i32)
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DEF_HELPER_2(xvaddsp, void, env, i32)
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DEF_HELPER_2(xvsubsp, void, env, i32)
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DEF_HELPER_2(xvmulsp, void, env, i32)
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DEF_HELPER_2(xvdivsp, void, env, i32)
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DEF_HELPER_2(efscfsi, i32, env, i32)
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DEF_HELPER_2(efscfui, i32, env, i32)
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@ -7307,14 +7307,17 @@ static void gen_##name(DisasContext * ctx) \
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GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
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#define VSX_LOGICAL(name, tcg_op) \
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static void glue(gen_, name)(DisasContext * ctx) \
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@ -10000,14 +10003,17 @@ GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
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GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
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GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
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GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
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GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
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GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
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GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
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GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
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GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
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GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
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GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
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GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
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GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
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#undef VSX_LOGICAL
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#define VSX_LOGICAL(name, opc2, opc3, fl2) \
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