mirror of https://github.com/proxmox/mirror_qemu
* Make named CPU models usable for qemu-{i386,x86_64}
* Fix backwards time with -icount auto -----BEGIN PGP SIGNATURE----- iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmSdRiQUHHBib256aW5p QHJlZGhhdC5jb20ACgkQv/vSX3jHroOqcwf9FGAqZ+0V34Y8XeXMu8Es3bFjEKG8 t3BpVNhTBOYDPvpshnPVx2I29nRT2opc1C4YkjMAv5/1nivj1kDM7hDObOSJQvqy 5FgTsJYqRtGj+J7uVBrspWZsP8BYeykKmXR6deBOPvCuw5nnLdDQ3dLV2F26lKUu lsFyEVbi4dzf8+TVuNIXEg7mVBYytjBQwBmmHgeOofeikjq9WEudr49mwJMCHyzl iXCatnctXGKZYSnp+eHIBiFRdSzjqdgrDRa0ysSqABoBI1pmkhyQKSay6cSjfG4n gFlqPF/i9RqAWpsQrM1IMGgPK39SrT2dYlHDJV2P/NEQrS6kLh2HoW/ArQ== =oj3B -----END PGP SIGNATURE----- Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging * Make named CPU models usable for qemu-{i386,x86_64} * Fix backwards time with -icount auto # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmSdRiQUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroOqcwf9FGAqZ+0V34Y8XeXMu8Es3bFjEKG8 # t3BpVNhTBOYDPvpshnPVx2I29nRT2opc1C4YkjMAv5/1nivj1kDM7hDObOSJQvqy # 5FgTsJYqRtGj+J7uVBrspWZsP8BYeykKmXR6deBOPvCuw5nnLdDQ3dLV2F26lKUu # lsFyEVbi4dzf8+TVuNIXEg7mVBYytjBQwBmmHgeOofeikjq9WEudr49mwJMCHyzl # iXCatnctXGKZYSnp+eHIBiFRdSzjqdgrDRa0ysSqABoBI1pmkhyQKSay6cSjfG4n # gFlqPF/i9RqAWpsQrM1IMGgPK39SrT2dYlHDJV2P/NEQrS6kLh2HoW/ArQ== # =oj3B # -----END PGP SIGNATURE----- # gpg: Signature made Thu 29 Jun 2023 10:51:48 AM CEST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [undefined] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: target/i386: emulate 64-bit ring 0 for linux-user if LM feature is set target/i386: ignore CPL0-specific features in user mode emulation target/i386: ignore ARCH_CAPABILITIES features in user mode emulation target/i386: Export MSR_ARCH_CAPABILITIES bits to guests icount: don't adjust virtual time backwards after warp Signed-off-by: Richard Henderson <richard.henderson@linaro.org>master
Richard Henderson
commit
4d541f63e9
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@ -47,7 +47,7 @@ static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
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}
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static uint64_t *idt_table;
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#ifdef TARGET_X86_64
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static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
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uint64_t addr, unsigned int sel)
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{
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@ -60,8 +60,10 @@ static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
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p[2] = tswap32(addr >> 32);
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p[3] = 0;
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}
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#ifdef TARGET_X86_64
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/* only dpl matters as we do only user space emulation */
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static void set_idt(int n, unsigned int dpl)
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static void set_idt(int n, unsigned int dpl, bool is64)
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{
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set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
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}
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@ -78,9 +80,13 @@ static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
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}
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/* only dpl matters as we do only user space emulation */
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static void set_idt(int n, unsigned int dpl)
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static void set_idt(int n, unsigned int dpl, bool is64)
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{
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set_gate(idt_table + n, 0, dpl, 0, 0);
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if (is64) {
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set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
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} else {
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set_gate(idt_table + n, 0, dpl, 0, 0);
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}
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}
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#endif
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@ -325,6 +331,9 @@ static void target_cpu_free(void *obj)
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void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
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{
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CPUState *cpu = env_cpu(env);
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bool is64 = (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) != 0;
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int i;
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OBJECT(cpu)->free = target_cpu_free;
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env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
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env->hflags |= HF_PE_MASK | HF_CPL_MASK;
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@ -332,15 +341,18 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
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env->cr[4] |= CR4_OSFXSR_MASK;
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env->hflags |= HF_OSFXSR_MASK;
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}
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#ifndef TARGET_ABI32
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/* enable 64 bit mode if possible */
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if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
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if (is64) {
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env->cr[4] |= CR4_PAE_MASK;
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env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
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env->hflags |= HF_LMA_MASK;
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}
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#ifndef TARGET_ABI32
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else {
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fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
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exit(EXIT_FAILURE);
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}
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env->cr[4] |= CR4_PAE_MASK;
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env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
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env->hflags |= HF_LMA_MASK;
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#endif
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/* flags setup : we activate the IRQs by default as in user mode */
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@ -379,27 +391,12 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
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PROT_READ|PROT_WRITE,
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MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
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idt_table = g2h_untagged(env->idt.base);
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set_idt(0, 0);
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set_idt(1, 0);
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set_idt(2, 0);
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set_idt(3, 3);
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set_idt(4, 3);
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set_idt(5, 0);
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set_idt(6, 0);
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set_idt(7, 0);
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set_idt(8, 0);
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set_idt(9, 0);
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set_idt(10, 0);
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set_idt(11, 0);
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set_idt(12, 0);
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set_idt(13, 0);
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set_idt(14, 0);
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set_idt(15, 0);
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set_idt(16, 0);
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set_idt(17, 0);
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set_idt(18, 0);
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set_idt(19, 0);
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set_idt(0x80, 3);
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for (i = 0; i < 20; i++) {
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set_idt(i, 0, is64);
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}
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set_idt(3, 3, is64);
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set_idt(4, 3, is64);
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set_idt(0x80, 3, is64);
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/* linux segment setup */
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{
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@ -259,11 +259,16 @@ static void icount_warp_rt(void)
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warp_delta = clock - timers_state.vm_clock_warp_start;
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if (icount_enabled() == 2) {
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/*
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* In adaptive mode, do not let QEMU_CLOCK_VIRTUAL run too
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* far ahead of real time.
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* In adaptive mode, do not let QEMU_CLOCK_VIRTUAL run too far
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* ahead of real time (it might already be ahead so careful not
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* to go backwards).
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*/
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int64_t cur_icount = icount_get_locked();
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int64_t delta = clock - cur_icount;
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if (delta < 0) {
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delta = 0;
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}
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warp_delta = MIN(warp_delta, delta);
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}
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qatomic_set_i64(&timers_state.qemu_icount_bias,
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@ -623,13 +623,25 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
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CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
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/* missing:
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CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
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/*
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* Kernel-only features that can be shown to usermode programs even if
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* they aren't actually supported by TCG, because qemu-user only runs
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* in CPL=3; remove them if they are ever implemented for system emulation.
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*/
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#if defined CONFIG_USER_ONLY
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#define CPUID_EXT_KERNEL_FEATURES (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER | \
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CPUID_EXT_X2APIC)
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#else
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#define CPUID_EXT_KERNEL_FEATURES 0
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#endif
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#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
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CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
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CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
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CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
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CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
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CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \
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CPUID_EXT_FMA)
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CPUID_EXT_FMA | CPUID_EXT_KERNEL_FEATURES)
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/* missing:
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CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
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CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID,
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@ -642,22 +654,66 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
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#define TCG_EXT2_X86_64_FEATURES 0
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#endif
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/*
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* CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable
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* in usermode or by 32-bit programs. Those are added to supported
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* TCG features unconditionally in user-mode emulation mode. This may
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* indeed seem strange or incorrect, but it works because code running
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* under usermode emulation cannot access them.
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*
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* Even for long mode, qemu-i386 is not running "a userspace program on a
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* 32-bit CPU"; it's running "a userspace program with a 32-bit code segment"
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* and therefore using the 32-bit ABI; the CPU itself might be 64-bit
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* but again the difference is only visible in kernel mode.
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*/
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#if defined CONFIG_LINUX_USER
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#define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR)
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#elif defined CONFIG_USER_ONLY
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/* FIXME: Long mode not yet supported for i386 bsd-user */
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#define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR
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#else
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#define CPUID_EXT2_KERNEL_FEATURES 0
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#endif
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#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
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CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
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CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
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CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES)
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CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \
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CPUID_EXT2_KERNEL_FEATURES)
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#if defined CONFIG_USER_ONLY
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#define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW
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#else
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#define CPUID_EXT3_KERNEL_FEATURES 0
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#endif
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#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
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CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \
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CPUID_EXT3_3DNOWPREFETCH)
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CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES)
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#define TCG_EXT4_FEATURES 0
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#if defined CONFIG_USER_ONLY
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#define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI)
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#else
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#define CPUID_SVM_KERNEL_FEATURES 0
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#endif
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#define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \
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CPUID_SVM_SVME_ADDR_CHK)
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CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES)
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#define TCG_KVM_FEATURES 0
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#if defined CONFIG_USER_ONLY
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#define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID
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#else
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#define CPUID_7_0_EBX_KERNEL_FEATURES 0
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#endif
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#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
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CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
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CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
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CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
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CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED)
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CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \
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CPUID_7_0_EBX_KERNEL_FEATURES)
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/* missing:
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CPUID_7_0_EBX_HLE
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CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */
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@ -672,7 +728,14 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
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CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \
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TCG_7_0_ECX_RDPID)
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#define TCG_7_0_EDX_FEATURES CPUID_7_0_EDX_FSRM
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#if defined CONFIG_USER_ONLY
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#define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \
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CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD)
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#else
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#define CPUID_7_0_EDX_KERNEL_FEATURES 0
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#endif
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#define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES)
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#define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \
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CPUID_7_1_EAX_FSRC)
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#define TCG_7_1_EDX_FEATURES 0
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@ -686,8 +749,17 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
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#define TCG_SGX_12_0_EBX_FEATURES 0
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#define TCG_SGX_12_1_EAX_FEATURES 0
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#if defined CONFIG_USER_ONLY
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#define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \
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CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \
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CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \
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CPUID_8000_0008_EBX_AMD_PSFD)
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#else
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#define CPUID_8000_0008_EBX_KERNEL_FEATURES 0
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#endif
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#define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \
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CPUID_8000_0008_EBX_WBNOINVD)
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CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES)
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FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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[FEAT_1_EDX] = {
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@ -1060,15 +1132,22 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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"rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
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"ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
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"taa-no", NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no",
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NULL, "fb-clear", NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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"pbrsb-no", NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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},
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.msr = {
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.index = MSR_IA32_ARCH_CAPABILITIES,
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},
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/*
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* FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which
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* cannot be read from user mode. Therefore, it has no impact
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> on any user-mode operation, and warnings about unsupported
|
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* features do not matter.
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*/
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.tcg_features = ~0U,
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},
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[FEAT_CORE_CAPABILITY] = {
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.type = MSR_FEATURE_WORD,
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@ -5463,7 +5542,15 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
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}
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#ifndef TARGET_X86_64
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if (w == FEAT_8000_0001_EDX) {
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r &= ~CPUID_EXT2_LM;
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/*
|
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* 32-bit TCG can emulate 64-bit compatibility mode. If there is no
|
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* way for userspace to get out of its 32-bit jail, we can leave
|
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* the LM bit set.
|
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*/
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uint32_t unavail = tcg_enabled()
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? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES
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: CPUID_EXT2_LM;
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r &= ~unavail;
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}
|
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#endif
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if (migratable_only) {
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|
|
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|||
|
|
@ -173,12 +173,14 @@ typedef struct DisasContext {
|
|||
#endif
|
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#if !defined(TARGET_X86_64)
|
||||
#define CODE64(S) false
|
||||
#define LMA(S) false
|
||||
#elif defined(CONFIG_USER_ONLY)
|
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#define CODE64(S) true
|
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#define LMA(S) true
|
||||
#else
|
||||
#define CODE64(S) (((S)->flags & HF_CS64_MASK) != 0)
|
||||
#endif
|
||||
#if defined(CONFIG_SOFTMMU) && !defined(TARGET_X86_64)
|
||||
#define LMA(S) false
|
||||
#else
|
||||
#define LMA(S) (((S)->flags & HF_LMA_MASK) != 0)
|
||||
#endif
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue